2475 - Why must I use a Primary Clock Input for a clock instead of a general purpose pin?
Lattice recommends always using Primary Clock (PCLK) inputs for clocks. An exception is when a clock input is routed directly to a single PLL then a dedicated PLL input should be used. If multiple PLLs are using the same input clock then a PCLK Input should be used and preferenced with a "USE PRIMARY <clock net>". This will route the clock to all PLLs while keeping the clock on Primary clock routing.
PCLK pins give the lowest injection delay, the highest performance, and the most stability. Lattice does not characterize general routing for clocks and over Process / Voltage / Temperature there can be a huge percentage of variation in jitter, duty cycle distortion, and delay in these clocks. Another factor is that the Lattice Diamond tools will change the route a generally routed clock uses when the HDL is changed or a different placement seed /options are used. As noted in our clocking application notes, any clock that uses general routing at any point cannot be used to clock the DDRs in our I/O logic blocks.
If you've run out of PCLK input pins then you can always use a dedicated PLL input and bypass the PLL. The output can then be preferenced to go use primary clock routing. This also adds some injection delay but you will not have the extreme variation that a general route will give you.
If you need to use a general route for a clock, you must use add "HOLD_MARGIN 500ps" on the frequency preference.