2598 - Can Lattice FPGAs use a general purpose I/O to assert it's own PROGRAMN pin?

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  Lattice recommends always using Primary Clock (PCLK) inputs for clocks. An exception is when a clock input is routed directly to a single PLL then a dedicated PLL input should be used. If multiple PLLs are using the same input clock then a PCLK Input ...

• 2453 - LatticeXP2: What does the I/O Type in Table 14-1 of TN1141 mean? For example, is the INITN pin only used as a bi-directional pin when CFG0 is high?<q1><q2></q2></q1>

  The I/O Type in Table 14-1 of TN1141 is for all the sysCONFIG pins during configuration. For the dual-purpose sysCONFIG pins, when they are used as general purpose I/Os after configuration, they can use any I/O type such as input, output and ...

• 655 - How is the Global Set Reset (GSR) used in a design? Do I need to use the GSR symbol or component in my design to use the GSRN pin for the MachXO device?

  For the Lattice MachXO device, all the registers in the device will be reset upon power-up of the device, provided the power-up sequence is clean. This will happen without any additional effort on the part of the user. The software will evaluate the ...

• 1666 - Power Manager II: Can I use the RESETb pin on a POWR1014 or POWR1220 to reset other parts of my circuit?

  The RESETb pin on an ispPAC-POWR1014 or ispPAC-POWR1220 is bidirectional (open drain with internal pull-up). Its primary function is to be used as an input so that one can reset the device after it has been powered up. The secondary function of this ...

• 1100 - How can I use the complimentary outputs in Lattice FPGAs? <br>

  Most Lattice FPGA devices provide a complimentary output feature which allows a single ended buffer to provide its compliment on a different pin without using any FPGA logic resources or user routing. To enable this complimentary path the user needs ...