2453 - LatticeXP2: What does the I/O Type in Table 14-1 of TN1141 mean? For example, is the INITN pin only used as a bi-directional pin when CFG0 is high?<q1><q2></q2></q1>

The I/O Type in Table 14-1 of TN1141 is for all the sysCONFIG pins during configuration. For the dual-purpose sysCONFIG pins, when they are used as general purpose I/Os after configuration, they can use any I/O type such as input, output and bi-directional. For example, the INITN pin is bi-directional open drain in the configuration mode. But it can be any I/O type as a general purpose I/O pin when the CFG0 pin is high. Please refer to Section Configuration Pins in TN1141 for the details.

Related Articles
7312 - Crosslink: How to implement OPENDRAIN on Bi-Directional I/O port in CrossLink device?
CrossLink I/O does not have OPENDRAIN support for bi-directional pins. This feature is limited by the device hardware itself. However, this product still offers OPENDRAIN support but only limited to output ports only.
3881 - Is it possible with the signal 'ENABLE_OUTPUT' of the primitive SB_IO (IO primitive of the iCE40) to create a bi-directional Low Voltage Differential Signalling (LVDS) IO?
No. the signal 'ENABLE_OUTPUT' of the primitive SB_IO (IO primitive of the iCE40) cannot be used to create a bi-directional LVDS IO. One has to use two separate pairs of IOs for LVDS Tx and LVDS Rx.
2598 - Can Lattice FPGAs use a general purpose I/O to assert it's own PROGRAMN pin?
Lattice does not recommend using the FPGA's general purpose I/O to assert its own PROGRAMN pin. There is risk the FPGA may not restart after the first attempt to assert the PROGRAMN pin. The PROGRAMN pin can inadvertently be pulled low, which can ...
5867 - ispMach400: In BSDL file, if any IOs are configured as "Input Only"; Does the device needs to be erased and re-programmed to bi-directional pin the same as the output?
The Input only IO, do not need to be erased and reprogrammed to be bi-di IO. Only output only IO needs it.
2994 - MachXO2: If the device is not yet programmed, it will be booted in Default Mode Feature Row. Will the INITn pin automatically be used as an input? And can I (accidently) block the configuration of the FPGA by pulling INITn low?
The INITn pin of MachXO2 device when erased (Default Mode Feature Row state) is disabled. So you should be protected from accidently blocking the configuration by pulling INITn low.

2453 - LatticeXP2: What does the I/O Type in Table 14-1 of TN1141 mean? For example, is the INITN pin only used as a bi-directional pin when CFG0 is high?<q1><q2></q2></q1>

2453 - LatticeXP2: What does the I/O Type in Table 14-1 of TN1141 mean? For example, is the INITN pin only used as a bi-directional pin when CFG0 is high?<q1><q2></q2></q1>

Related Articles

7312 - Crosslink: How to implement OPENDRAIN on Bi-Directional I/O port in CrossLink device?

3881 - Is it possible with the signal 'ENABLE_OUTPUT' of the primitive SB_IO (IO primitive of the iCE40) to create a bi-directional Low Voltage Differential Signalling (LVDS) IO?

2598 - Can Lattice FPGAs use a general purpose I/O to assert it's own PROGRAMN pin?

5867 - ispMach400: In BSDL file, if any IOs are configured as "Input Only"; Does the device needs to be erased and re-programmed to bi-directional pin the same as the output?

2994 - MachXO2: If the device is not yet programmed, it will be booted in Default Mode Feature Row. Will the INITn pin automatically be used as an input? And can I (accidently) block the configuration of the FPGA by pulling INITn low?