7139 - All Nexus: Can user drive PLL dedicated clock input complement pin (GPLL_C) as the single-ended reference clock for the PLL?

• Related Articles

• What is the difference between PCLKT and PLLT as dedicated PLL reference clock?

  Both PCLKT and PLLT are legal pin to use as PLL reference clock however there are differences on the clock paths that should take note in designing certain applications. PCLKT Pin: Provides a direct connection to the global and regional clock ...

• 2116 - Lattice ECP3: The availability and cost of a 1.5V clock driver make it an unattractive solution for driving the reference clock input of the DDR3 memory interface, are there any alternatives?

  Several alternatives can be used to drive the LatticeECP3 DDR3 reference clock input: 1. Use an LVDS clock driver and connect directly to the DDR3-dedicated PLL input pair. LVDS25 is a compatible I/O type that can be used in a 1.5V VCCIO bank. This ...

• 2475 - Why must I use a Primary Clock Input for a clock instead of a general purpose pin?

  Lattice recommends always using Primary Clock (PCLK) inputs for clocks. An exception is when a clock input is routed directly to a single PLL then a dedicated PLL input should be used. If multiple PLLs are using the same input clock then a PCLK Input ...

• 2005 - LatticeECP3:  How do I select between the two Vol Max values 0.4V, or 0.2V documented in the LatticeECP3 device datasheet sysI/O Single-Ended DC Electrical Characteristics?  

  Vol Max is not a user configurable setting. For any of the LVCMOS pin configurations, under normal operating conditions Vol is specified to be a a maximum of 0.4V regardless of the drive strength that the pin was configured. If the current draw falls ...

• 7055 - All Nexus: What pins are preferred for output clocks?

  For input clocks, we can only used dedicated clock pins, PCLK or GPLL input pins for PLL reference clock. For output clocks, any IO pin can be used. There is no restriction for this.