1946 - [LatticeECP3/LatticeECP2/MachXO2/XP2] Are there hardware resources that helps me to achieve my input HOLD requirements?
Yes, there are such resources in select Lattice devices. There are three different resources that you can use to do this. They are:
1). FIXEDDELAY: Supported in ECP3, MachXO2, and XP2 devices.
2). DELAYC: Supported in ECP3 devices.
3). DELAYB: Supported in ECP2/M, ECP3, and XP2 devices.
All of these resources compensate your input HOLD requirements by adding specific amount of delay in your data input path into your device. By doing so, the HOLD requirement is effectively decreased. However, doing this will also affect your SETUP requirement (i.e. increase in the SETUP time by the same decrease in the HOLD time). So, it is advisable that you consider both SETUP and HOLD times effects when adding these delays. A typical usage of these resources is when you have plenty of timing closure margin in your SETUP time requirement, but you are not meeting the HOLD requirement by a margin smaller than that of the SETUP time (i.e. SETUP meeting margin > HOLD not-met margin).
The examples below describes each resource and how they are enabled. The delay values used below are values for ECP3. For the delay values of other devices, please run a test case for the desired resources in the software tools and generate the test case's TRCE report. The TRCE report contains the delay values for each device.
*************
FIXEDDELAY
*************
FIXEDDELAY inserts 1300ps of delay into the data path, which decreases the HOLD time and increases the SETUP time by that amount. As the name implies, this delay is fixed.
The following Verilog code inserts FIXEDDELAY into an input path before the data input register:
// Begin code
input clk,rst;
input b0/* synthesis syn_useioff = 1 FIXEDDELAY = TRUE */;
input b1, b2;
wire [2:0] b = {b2,b1,b0};
reg [2:0] bx;
always @(posedge clk or posedge rst)
if(rst)
bx <= 3'h0;
else
bx <= b;
// End code
Note that inserting FIXEDDELAY is performed using an HDL attribute. Also note that you can't insert it to selective I/O bus index. The workaround for this is to declare a single input and attach the HDL attribute followed by concatenating the inputs into a bus.
The following TRCE report illustrates a HOLD analysis without FIXEDDELAY:
========================================
Preference: INPUT_SETUP PORT "b0" 1.000000 ns HOLD -0.500000 ns CLKPORT "clk" ;
1 item scored, 1 timing error detected.
----------------------------------------------------------------------
Error: The following path exceeds requirements by 1.889ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Port Pad b0
Destination: FF Data in bx_0io_0 (to clk_c +)
Min Data Path Delay: 0.200ns (100.0% logic, 0.0% route), 1 logic levels.
Max Clock Path Delay: 0.909ns (27.5% logic, 72.5% route), 1 logic levels.
IOL_R29B attributes: FINE=FDEL0
Constraint Details:
0.200ns delay b0 to b0_MGIOL plus
-0.500ns hold offset b0 to clk (totaling -0.300ns) violates
0.909ns delay clk to b0_MGIOL plus
0.680ns DI_HLD requirement (totaling 1.589ns) by 1.889ns
The following TRCE report illustrates the effect of FIXEDDELAY on the HOLD path:
========================================
Preference: INPUT_SETUP PORT "b0" 1.000000 ns HOLD -0.500000 ns CLKPORT "clk" ;
1 item scored, 1 timing error detected.
----------------------------------------------------------------------
Error: The following path exceeds requirements by 0.589ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Port Pad b0
Destination: FF Data in bx_0io_0 (to clk_c +)
Min Data Path Delay: 0.200ns (100.0% logic, 0.0% route), 1 logic levels.
Max Clock Path Delay: 0.909ns (27.5% logic, 72.5% route), 1 logic levels.
IOL_R29B attributes: FINE=FDEL0
Constraint Details:
0.200ns delay b0 to b0_MGIOL plus
-0.500ns hold offset b0 to clk (totaling -0.300ns) violates
0.909ns delay clk to b0_MGIOL plus
-0.620ns DI_HLD requirement (totaling 0.289ns) by 0.589ns
Note from that the 1300ps difference in the DI_HLD requirement.
*************
DELAYC
*************
DELAYC is similar to FIXEDDELAY because it inserts 1300ps of delay into the data path, which decreases the HOLD time and increases the SETUP time by that amount. Like FIXEDDELAY, DELAYC is fixed.
The following Verilog code inserts DELAYC into an input path before the data input register:
// Begin code
input b0, b1, b2;
wire [2:0] bx;
wire b_temp;
DELAYC my_delay1(.Z(b_temp), .A(b1));
// IO Registers
IFS1P3IX b0_reg(.Q(bx[0]), .SP(1'b1), .CD(rst), .SCLK(clk), .D(b_temp));
IFS1P3IX b1_reg(.Q(bx[1]), .SP(1'b1), .CD(rst), .SCLK(clk), .D(b1));
IFS1P3IX b2_reg(.Q(bx[2]), .SP(1'b1), .CD(rst), .SCLK(clk), .D(b2));
// End code
Note that to use DELAYC, you will need to use the DELAYC primitive.
The effect of DELAYC in the TRCE report is exactly the same as that of FIXEDDELAY (see above).
*************
DELAYB
*************
Unlike the previous two resources, DELAYB allows you to insert a delay amount between 0ps to 675ps at 45ps increments (i.e. 16 different values). This feature allows you to find the optimal value to meet both SETUP and HOLD requirements. Like all the other previous resources, the chosen delay amount will decrease and increase your HOLD time and SETUP time respectively by that same amount of delay.
The following verilog code inserts DELAYB into an input path before the data input register:
// Begin code
input b0, b1, b2;
wire [2:0] bx;
wire [3:0] b_temp;
DELAYB my_delay0(.Z(b_temp[0]), .DEL3(1'b0), .DEL2(1'b0), .DEL1(1'b0), .DEL0(1'b1), .A(b0));
DELAYB my_delay1(.Z(b_temp[1]), .DEL3(1'b0), .DEL2(1'b0), .DEL1(1'b0), .DEL0(1'b0), .A(b1));
DELAYB my_delay2(.Z(b_temp[2]), .DEL3(1'b1), .DEL2(1'b1), .DEL1(1'b1), .DEL0(1'b1), .A(b2));
// IO Registers
IFS1P3IX b0_reg(.Q(bx[0]), .SP(1'b1), .CD(rst), .SCLK(clk), .D(b_temp[0]));
IFS1P3IX b1_reg(.Q(bx[1]), .SP(1'b1), .CD(rst), .SCLK(clk), .D(b_temp[1]));
IFS1P3IX b2_reg(.Q(bx[2]), .SP(1'b1), .CD(rst), .SCLK(clk), .D(b_temp[2]));
// End code
Note that in the above example, each input has a unique delay value. The delay value is determined by the value of DEL[3:0]. Also note that DELAYB is inserted using primitive instantiation.
The following TRCE report illustrates the effect of DELAYC with tap value of 1 (i.e. DEL[3:0] = 4'b0001) on the HOLD path:
========================================
Preference: INPUT_SETUP PORT "b0" 1.000000 ns HOLD -0.500000 ns CLKPORT "clk" ;
1 item scored, 1 timing error detected.
----------------------------------------------------------------------
Error: The following path exceeds requirements by 1.844ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Port Pad b0
Destination: FF Data in b0_reg (to clk_c +)
Min Data Path Delay: 0.200ns (100.0% logic, 0.0% route), 1 logic levels.
Max Clock Path Delay: 0.909ns (27.5% logic, 72.5% route), 1 logic levels.
IOL_R26EC attributes: FINE=FDEL1
Constraint Details:
0.200ns delay b1 to b0_MGIOL plus
-0.500ns hold offset b1 to clk (totaling -0.300ns) violates
0.909ns delay clk to b0_MGIOL plus
0.635ns DI_HLD requirement (totaling 1.544ns) by 1.844ns
Note the 45ps difference between the DI_HLD above and that of without any delay.
**********
In short, depending on your requirements and situation, you can use either FIXEDDELAY, DELAYC, or DELAYB.
For more information on these resources, click "Help" -> "Lattice Diamond Help", and use the keywords "FIXEDDELAY", "DELAYC", or "DELAYB".