725 - Does the MachXO device family support true LVDS buffers?<br>

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• 1605 - Does default IO behavior change from device family to device family?<BR>

  The IO behavior of each Lattice device family could be unique. Some of the device families support pull and bus keeper circuitry for each individual pin, some support such function on a global basis, while others have different pull condition for ...

• 2356 - LatticeECP3: Can I lock the dual-link 7:1 LVDS pins to the left and right sides of a LatticeECP3-17EA device? <br>

  Description: Yes. Lattice recommends placing the 7:1 LVDS RX or TX pins on the left or right side of a LatticeECP3 device. If they are locked to both sides, the edge clock should go to both sides through dedicated routing resources. A LatticeECP3 EA ...

• 2330 - LatticeECP3: Can LatticeECP3 devices support sub-LVDS IO?

  Description: LatticeECP3 devices do not directly support sub-LVDS IO. But LatticeECP3 can support sub-LVDS IO with an external termination circuit. Please refer to Sub-LVDS Signaling Using Lattice Devices (FPGA-TN-02028) Technical Note available on ...

• 880 - The LatticeXP2 device does not have a sub-LVDS output type, can I still drive sub-LVDS inputs with the LatticeXP2? <BR>

  Situation: An application uses the LatticeXP2 device and needs the sub-LVDS output type. Solution: Given that sub-LVDS signaling requires Vod from 100mv (min) to 200mv (max) and Vcm from +0.75v (min) to +1.05v (max), the sub-LVDS output type can be ...

• 3862 - iCE40: How to&nbsp;identify true (positive)&nbsp;and&nbsp;complementary (negative)&nbsp;ball functions for&nbsp;Low Voltage Differential Signaling (LVDS) inputs in iCE40 device?

  The differential signals ending with 'B' in the Pinout file represent the positive end, and the differential signals ending with 'A' represent the negative end. For example, in the Pinout file, IOL_3A and IOL_3B are differential pins (DPIO). So, ...