6323 - MachXO3: Can the HCSL to LVDS Translation be done in MachXO3 Device?

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• 725 - Does the MachXO device family support true LVDS buffers?<br>

  The larger two devices (LCMXO1200 & LCMXO2280) in the MachXO family support True LVDS I/O. To set up "true LVDS" on the input side, connect a 100 ohm terminating resistor across the 'true' and 'compliment' input terminals. On the output side, no ...

• 619 - What is the detailed power-up sequence for a MachXO device?

  The following is the power-up sequence for a MachXO device: - All IOs trisate with a weak pull up - POR (Power On Reset) for internal circuitry asserted - Vcc and Vccaux reach minimum recommended datasheet levels - POR (Power On Reset) for internal ...

• 739 - What is the default I/O state in a blank MachXO device?

  The silicon default of a bulk-erased MachXO device is as follows: Inputs are enabled, and referenced to Vccio. Buskeepers default to pullup. Outputs are tri-stated and default to 8ma at Vccio=1.8V and slow slew.

• 2330 - LatticeECP3: Can LatticeECP3 devices support sub-LVDS IO?

  Description: LatticeECP3 devices do not directly support sub-LVDS IO. But LatticeECP3 can support sub-LVDS IO with an external termination circuit. Please refer to Sub-LVDS Signaling Using Lattice Devices (FPGA-TN-02028) Technical Note available on ...

• 880 - The LatticeXP2 device does not have a sub-LVDS output type, can I still drive sub-LVDS inputs with the LatticeXP2? <BR>

  Situation: An application uses the LatticeXP2 device and needs the sub-LVDS output type. Solution: Given that sub-LVDS signaling requires Vod from 100mv (min) to 200mv (max) and Vcm from +0.75v (min) to +1.05v (max), the sub-LVDS output type can be ...