2356 - LatticeECP3: Can I lock the dual-link 7:1 LVDS pins to the left and right sides of a LatticeECP3-17EA device? <br>

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• 880 - The LatticeXP2 device does not have a sub-LVDS output type, can I still drive sub-LVDS inputs with the LatticeXP2? <BR>

  Situation: An application uses the LatticeXP2 device and needs the sub-LVDS output type. Solution: Given that sub-LVDS signaling requires Vod from 100mv (min) to 200mv (max) and Vcm from +0.75v (min) to +1.05v (max), the sub-LVDS output type can be ...

• 5846 - All Devices: Can Lattice FPGA IO pins be left Floating?

  Floating IO pin is not recommended. If IO pins are left floating, then the input transistors might fall outside of the saturation or cut-off region. As a result, the device could draw additional current and increase the device's power consumption. If ...

• 879 - LatticeXP2: How can I drive mini-LVDS output on LatticeXP2 if mini-LVDS IO standard is not available? <br>

  If user's design is using 50 ohm PCB trace and cable impedances, user can set the LatticeXP2 IO output type to LVDS and this will produce 400mv peak signal swing at the receiver's 100 ohm termination with proper common mode output voltage. The ...

• 5869 - Platform Manager2 and ASC devices: Can VMON and VMONGS pins be left floating when they are not in use?

  VMONx/VMONGS pins can be left floating when not in use. But it's also a good practice to ground the VMONGS pin and put a pull-down on the VMON pin to make it easier to do some workaround if you decided to use the VMONx/VMONGS pins again.

• 843 - What can I do to maximize the emulated LVDS data rate? <br>

  Emulated LVDS will have maximum data rate near the device FMAX_IO frequency value if: the IOs are complimentary LVCMOS outputs (or have low timing skew) the IOs have similar rise and fall times the emulated LVDS output resistor network is placed ...