843 - What can I do to maximize the emulated LVDS data rate? <br>

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• 2895 - LatticeXP2: Why is the LVDS data not received correctly when the fail-safe resistors are added?

  The problem may be related to the big fail-safe bias voltage (Vfsb) with the small fail-safe resistors that can cause the distortion on the duty of the LVDS input and increase jitter. It will worsen the correct sampling of the LVDS RX data especially ...

• 883 - How to change the emulated LVDS resistor network to get other output voltage levels?

  The following table lists 1% resistor values to use when the VCCIO is set to 2.5V and the IO output current setting is 8ma: Differential mV Rseries Rparallel 191 301 118 217 261 121 266 210 127 310 178 133 357 150 140 417 124 150 478 105 162 ...

• 2110 - LatticeECP3: How to fix <i>netsanitycheck </i>error when dynamic clock selector drives DDR (Double Data Rate) primitive components?<br>

  LatticeECP3 device requires dedicated or primary clock resources to drive DDR (Double Data Rate) primitive components. The clock nets from the clock input pads to the destination DDR component must use pure primary or dedicated clock nets. If you ...

• 880 - The LatticeXP2 device does not have a sub-LVDS output type, can I still drive sub-LVDS inputs with the LatticeXP2? <BR>

  Situation: An application uses the LatticeXP2 device and needs the sub-LVDS output type. Solution: Given that sub-LVDS signaling requires Vod from 100mv (min) to 200mv (max) and Vcm from +0.75v (min) to +1.05v (max), the sub-LVDS output type can be ...

• 1825 - What is the recommended slew rate with less duty cycle variations? <br>

  The FAST or SLOW slew can cause as much as 5% duty cycle variation depending on the frequency and the load. The general recommendation is to use FAST slew rate for frequencies higher than MHz. At higher frequencies, FAST slew will show a more ...