2895 - LatticeXP2: Why is the LVDS data not received correctly when the fail-safe resistors are added?

2895 - LatticeXP2: Why is the LVDS data not received correctly when the fail-safe resistors are added?

The problem may be related to the big fail-safe bias voltage (Vfsb) with the small fail-safe resistors that can cause the distortion on the duty of the LVDS input and increase jitter. It will worsen the correct sampling of the LVDS RX data especially for higher data rate. The Vfsb should just make the LVDS output high along with the noise margin. We can increase the value of the fail-safe pull-up and pull-down resistors to about 1.7Kohm. If so, we can reduce the Vfsb to about 70mV that will be detected as high for LatticeXP2's LVDS input buffer. And it still has the noise margin to avoid the problem of the signal integrity.