384 - <p>Why are termination resistors required&nbsp;for DDR2 and DDR3 when the&nbsp;LatticeECP3 has an on-die termination (ODT) feature?</p>

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• 2263 - LatticeECP3:&nbsp; What is the proper use of termination resistors and internal coupling with the Lattice Serdes?

  Current Mode Logic (CML) buffers are used as the common interface to the SERDES/PCS. Internal input and output terminations are provided to simplify board level interfacing and AC coupling capacitors are available within the CML receiver. These allow ...

• 6523 - Certus-NX: Can LVDS IOs be used on banks 6 &amp; 7 and what limitations are there? Are inputs to be LVDS25E or does that just apply to outputs? For inputs, on banks 6 &amp; 7, are the 100 termination resistors available?

  Bank 3, 4, and 5 are the High Speed Banks that support True LVDS. For Bank 6 and 7, although pins can operate through differential pair, its speed is limited to LVCMOS (Input and Output) or LVDS25E (output). Single ended termination with programmable ...

• 128 - What are VCC(VDD)IB and VCC(VDD)OB supply connections&nbsp;used for on LatticeECP2M/3 and LatticeSC/M devices?

  Current-Mode Logic (CML) input and output buffers must be terminated for proper operation. CML uses true double termination. Rather than LVDS which is only terminated at the receiver. This means that any signal reflection back to the source reflects ...

• 2157 - [LatticeECP3] Will the LatticeECP3's read datavalid generation circuit work properly when I remove the VTT termination from the DQS pad?

  The datavalid generation circuit works properly as long as you provide the READ pulse input to the DQSBUF block in the right timing. LatticeECP3 devices have preamble detection function which is a level detection circuit instead of edge detection. ...

• 2895 - LatticeXP2: Why is the LVDS data not received correctly when the fail-safe resistors are added?

  The problem may be related to the big fail-safe bias voltage (Vfsb) with the small fail-safe resistors that can cause the distortion on the duty of the LVDS input and increase jitter. It will worsen the correct sampling of the LVDS RX data especially ...