5846 - All Devices: Can Lattice FPGA IO pins be left Floating?
Floating IO pin is not recommended. If IO pins are left floating, then the input transistors might fall outside of the saturation or cut-off region. As a result, the device could draw additional current and increase the device's power consumption. If the device is within the permitted junction temperature range, this leakage current will not have to affect the functionality of the design. However, if this current is causing the device to go out of the junction temperature range, then it may affect device performance. Additionally, if left floating, these pins are apt to switch (they behave similarly to antennas) which can inject noise into the device.
The I/O pins which are not used in the design normally do not need to be grounded or connected anywhere externally. By default, Lattice device I/O is either Pull-Up or Pull-Down, the internal pull-up/pull-down will bias the pin and prevent it from floating.
For the I/O pins that are used in the design: If the inputs are always driven (either High or Low), then no need for external or internal pull modes. If the inputs are driven from a source that tristate its output pins, or if not connected (cable/board is not connected), then there has to be pull mode (HIGH or LOW depending on the application) included at the input, either internally or externally. You must only tie-off the input pins on the PCB if you intentionally disable the internal pull-up or pull-down. You should connect the pins on the PCB to VCCIO, GND, or a static signal for better noise immunity.