5869 - Platform Manager2 and ASC devices: Can VMON and VMONGS pins be left floating when they are not in use?

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• 1433 - Platform Manager/Power Manger II: How do I protect VMON input pins from noise or accidental spikes?

  The absolute maximum input voltage for the VMON input pins is 6V. Any inadvertent stresses beyond this limit will damage the device. Thus, protection circuits (like using a 5.1V shunt Zener diode) are recommended to guard the VMON input pins against ...

• 5846 - All Devices: Can Lattice FPGA IO pins be left Floating?

  Floating IO pin is not recommended. If IO pins are left floating, then the input transistors might fall outside of the saturation or cut-off region. As a result, the device could draw additional current and increase the device's power consumption. If ...

• 2377 - Platform Manager 2 & L-ASC10: What are the allowed input currents for the Power Manager II VMON and digital inputs? Is there a specific recommendation for protecting those inputs?

  The VMON inputs need to be protected according to the voltage limits mentioned in the datasheet (<5.9V). This information is contained in the Recommended Operating Conditions table (Page 5 of the POWR1014/A datasheet) ...

• 1402 - Platform Manager 2 &amp; L-ASC10: Do you have any examples of logging power supply faults?

  We have several reference designs for Power Manager devices that show how to detect a power supply fault (over voltage or under voltage) and save the data in a SPI memory. Using a current to voltage circuit the fault could also be an over current. ...

• 2356 - LatticeECP3: Can I lock the dual-link 7:1 LVDS pins to the left and right sides of a LatticeECP3-17EA device? <br>

  Description: Yes. Lattice recommends placing the 7:1 LVDS RX or TX pins on the left or right side of a LatticeECP3 device. If they are locked to both sides, the edge clock should go to both sides through dedicated routing resources. A LatticeECP3 EA ...