Lattice Diamond: How do i make sure that Write Enable and Chip Enable for my EBR to be inactive to avoid EBR contents glitch and corruption?

Description:

Users may encounter an INFO message shown below if there design has an EBR and GSR is disabled.

chipcheck: INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.

Solution:

The INFO message above indicates that the WE and CS signals should be grounded to make sure that there will be no glitch or corruption on EBR contents. You can do this by fully grounding these signals from the EBR or by making sure that in your reset signals these signals are initialized, given this you must have the reset asserted after usermode for atleast 2-3 clock cycles.

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Lattice Diamond: How do i make sure that Write Enable and Chip Enable for my EBR to be inactive to avoid EBR contents glitch and corruption?

Lattice Diamond: How do i make sure that Write Enable and Chip Enable for my EBR to be inactive to avoid EBR contents glitch and corruption?

Related Articles

7331 - Diamond/Radiant: How to disable GSR in Lattice Diamond/Radiant?

1719 - LatticeECP3: How do I&nbsp;get the Lattice FPGA&nbsp;DCS to switch from an inactive clock to an active one in simulation?

655 - How is the Global Set Reset (GSR) used in a design? Do I need to use the GSR symbol or component in my design to use the GSRN pin for the MachXO device?

1100 - How can I use the complimentary outputs in Lattice FPGAs?

2945 - Power Manager II: Why do I see a short (150ns or longer) logic zero glitch on my Power Manager Supervisory Equation open-drain-output shortly after power-up?

1719 - LatticeECP3: How do I get the Lattice FPGA DCS to switch from an inactive clock to an active one in simulation?