7331 - Diamond/Radiant: How to disable GSR in Lattice Diamond/Radiant?
To fully disable GSR in Lattice Diamond and Radiant:
1. Project=>Active Strategy=>Synplify Pro settings/LSE Settings(depending on the synthesizer you are using):
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Lattice Diamond: How do i make sure that Write Enable and Chip Enable for my EBR to be inactive to avoid EBR contents glitch and corruption?
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655 - How is the Global Set Reset (GSR) used in a design? Do I need to use the GSR symbol or component in my design to use the GSRN pin for the MachXO device?
For the Lattice MachXO device, all the registers in the device will be reset upon power-up of the device, provided the power-up sequence is clean. This will happen without any additional effort on the part of the user. The software will evaluate the ...
975 - What is the state of Flip Flop outputs at power-up? The reset pins of my design registers are tied to neither GSR nor LSR
Even if you do not use the GSR/LSR logic in RTL, GSR is always used during bitstream download. During bitstream download all flip flops are held at reset until the download is completed. So, the state of a register's Q output is always '0' or LOW at ...
5846 - All Devices: Can Lattice FPGA IO pins be left Floating?
Floating IO pin is not recommended. If IO pins are left floating, then the input transistors might fall outside of the saturation or cut-off region. As a result, the device could draw additional current and increase the device's power consumption. If ...
1628 - Power Manager II: When using the trim functions of a POWR6AT6, or POWR1220 what happens if I separately disable the LDO or DC-to-DC converter being controlled?
If you disable an LDO or DC-to-DC converter being trimmed bya POWR6AT6 or POWR1220, their trim circuitry will still attempt to perform the trim operation, except that it will now see '0' V as the feedback voltage. This will result in the TRIM output ...