Description:
This is usually the result of setting the Reset level in the PINS window to Set Low / Don't Care; combined with the logic of the Supervisory Equation setting the output High. If the logic High condition passes through more than a single macrocell; then the glitch can be wider than 4us. In fact the glitch will be multiples of 4us for each stage of logic used beyond the first macrocell or register.
This is further explained by looking at both AN6073 and the Datasheet startup waveforms. Before reset, the output is High-Z and goes High if an external pull-up is connected. At reset, the output goes Low. In the data sheet the TSTART parameter has no minimum value and the first rising edge of CPLDCLK will clock the data value into the Supervisory Logic register. Thus, after Reset, the output will only be Low for the TSTART time.
Solution:
To prevent occurrences of this type of glitch; make the reset-level in the PINS window match the initial condition of the Supervisory Logic.