2933 - Power Manager II: Why do I see a short (150ns or longer) logic zero glitch on my Power Manager open-drain output at the beginning of the sequence?

Description:

This is usually the result of setting the Reset level in the PINS window to Set Low / Don't Care; combined with the first step of the sequence setting the output High. If the output is set High in the second step of the sequence; then the glitch will be just a bit wider than 4us. If the output is set high after the "Wait for AGOOD" step, then the width of the pulse can be up to 2.5ms.

This is further explained by looking at both AN6073 and the Datasheet startup waveforms. Before reset, the output is High-Z and goes High if an external pull-up is connected. At reset, the output goes Low. In the data sheet the T_START parameter has no minimum value and the first rising edge of CPLDCLK will engage the first step of the sequence. Thus, after Reset, the output will only be Low for the T_START time.

Solution:

To prevent occurrences of this type of glitch; set the output levels in the first step in the sequencer control section to match the reset-level in the PINS window.

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2933 - Power Manager II: Why do I see a short (150ns or longer) logic zero glitch on my Power Manager open-drain output at the beginning of the sequence?

2933 - Power Manager II: Why do I see a short (150ns or longer) logic zero glitch on my Power Manager open-drain output at the beginning of the sequence?

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2945 - Power Manager II: Why do I see a short (150ns or longer) logic zero glitch on my Power Manager Supervisory Equation open-drain-output shortly after power-up?

2507 - Lattice Power Manager II: In the Power Manager device, is the&nbsp;output impedance of HVOUT port (in open drain mode)&nbsp;equal to that of the&nbsp;OUT port?

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