2390 - LatticeECP3: Can all Tx PLL clocks of SERDES drive the primary clock routing directly?<br>

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• 2381 - LatticeECP3: How do I implement an external reference clock for SERDES?<br>

  Description: The sources of external reference clocks for SERDES can be: Primary Clock pad (PCLK) FPGA PLL Since the extra jitter caused by the FPGA resources to route the clock to the SERDES will be passed onto the transmit data, care must be taken ...

• 1152 - Will Lattice FPGA's allow me to drive&nbsp;primary clock signal also drive on the edge clock?

  Yes, can do this for the for the LatticeECP2/M, LatticeECP3, and LatticeSC/M FPGA devices. If you have a Primary clock signal that you also want to use to drive an edge clock, use the "PRIMARY2EDGE" preference. This will insure that the software ...

• What is the difference between PCLKT and PLLT as dedicated PLL reference clock?

  Both PCLKT and PLLT are legal pin to use as PLL reference clock however there are differences on the clock paths that should take note in designing certain applications. PCLKT Pin: Provides a direct connection to the global and regional clock ...

• 2475 - Why must I use a Primary Clock Input for a clock instead of a general purpose pin?

  Lattice recommends always using Primary Clock (PCLK) inputs for clocks. An exception is when a clock input is routed directly to a single PLL then a dedicated PLL input should be used. If multiple PLLs are using the same input clock then a PCLK Input ...

• 970 - How do I implement edge clock routing from a Primary IO (PIO) in a LatticeECP2/M device? <BR>

  You need to locate an input buffer in a dedicated site that supports direct access to the edge clock spine. This applies to PIOs that clock special elements like IDDR/ODDR as well as CLKDIV blocks. Typically, you need to specifiy an EDGE preference ...