2381 - LatticeECP3: How do I implement an external reference clock for SERDES?<br>

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• 2645 - ECP3: How does the Clock Data Recovery (CDR) Loss of Lock pin on the LatticeECP3 behave when the reference clock is stopped?<br>

  The CDR Lock detection circuit is a digital counter based on the reference clock. If the clock is removed while the CDR is lock, CDR Loss of Lock will continue to indicate lock status (last registered state). If the input to the Receiver is removed, ...

• 2390 - LatticeECP3: Can all Tx PLL clocks of SERDES drive the primary clock routing directly?<br>

  Description: No, only the Tx PLL half/full rate clocks in channel 0 of each SERDES quad may drive the primary clock routing directly. Eight primary clocks(CLK0~CLK7) may be used for LatticeECP3 devices. To drive the primary clock routing directly: ...

• 970 - How do I implement edge clock routing from a Primary IO (PIO) in a LatticeECP2/M device? <BR>

  You need to locate an input buffer in a dedicated site that supports direct access to the edge clock spine. This applies to PIOs that clock special elements like IDDR/ODDR as well as CLKDIV blocks. Typically, you need to specifiy an EDGE preference ...

• 1563 - How can I implement the tri-status buffer driven by the output of ODDRXD1 in ECP3 ?<br>

  To implement the tri-status buffer driven by the output of ODDRXD1(the output DDR for DDR generic mode in X1 gearing), you should use OFD1S3AX(a primitive used to implement DDR and DDR2 DQ tri-state) to generate OE signal for the tri-status buffer, ...

• What is the difference between PCLKT and PLLT as dedicated PLL reference clock?

  Both PCLKT and PLLT are legal pin to use as PLL reference clock however there are differences on the clock paths that should take note in designing certain applications. PCLKT Pin: Provides a direct connection to the global and regional clock ...