2645 - ECP3: How does the Clock Data Recovery (CDR) Loss of Lock pin on the LatticeECP3 behave when the reference clock is stopped?<br>

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• 2381 - LatticeECP3: How do I implement an external reference clock for SERDES?<br>

  Description: The sources of external reference clocks for SERDES can be: Primary Clock pad (PCLK) FPGA PLL Since the extra jitter caused by the FPGA resources to route the clock to the SERDES will be passed onto the transmit data, care must be taken ...

• 2253 - LatticeECP3:&nbsp; I have a DCS feeding a PLL and when it switches in simulation my PLL loses lock.<br>

  The PLL simulation model will lose lock when there is a difference between the input and the feedback clocks. This is due to the difficulty in modelling the actual PLL hardware. TN1178 recommends that you do not switch the input clock to the PLL as ...

• What is the difference between PCLKT and PLLT as dedicated PLL reference clock?

  Both PCLKT and PLLT are legal pin to use as PLL reference clock however there are differences on the clock paths that should take note in designing certain applications. PCLKT Pin: Provides a direct connection to the global and regional clock ...

• 1997 - Power Manager II: What is the buffer type for the POWR1220AT8 JTAG TDO pin and what voltage should the pull-up resistor be tied to for this pin?<br>

  The JTAG TDO pin is an LVCMOS output that is referenced to the voltage applied to the VCCJ pin. The voltage reference for this pin is shown in note 1 to the Digital Specifications table on page 1-11 of the ispPAC-POWR1220AT8 data sheet. There is no ...

• 2110 - LatticeECP3: How to fix <i>netsanitycheck </i>error when dynamic clock selector drives DDR (Double Data Rate) primitive components?<br>

  LatticeECP3 device requires dedicated or primary clock resources to drive DDR (Double Data Rate) primitive components. The clock nets from the clock input pads to the destination DDR component must use pure primary or dedicated clock nets. If you ...