7721 - All Nexus: Why does the PLL output clock period not accurately show on the simulation?

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• What is the difference between PCLKT and PLLT as dedicated PLL reference clock?

  Both PCLKT and PLLT are legal pin to use as PLL reference clock however there are differences on the clock paths that should take note in designing certain applications. PCLKT Pin: Provides a direct connection to the global and regional clock ...

• 7055 - All Nexus: What pins are preferred for output clocks?

  For input clocks, we can only used dedicated clock pins, PCLK or GPLL input pins for PLL reference clock. For output clocks, any IO pin can be used. There is no restriction for this.

• 7139 - All Nexus: Can user drive PLL dedicated clock input complement pin (GPLL_C) as the single-ended reference clock for the PLL?

  For single-ended clock input to the PLL, user must use the PLL dedicated clock input true pins (GPLL_T). This is similar to the limitation with PCLK_T pins for clock pins. Complement pins must only be used for differential signaling.

• 2253 - LatticeECP3:&nbsp; I have a DCS feeding a PLL and when it switches in simulation my PLL loses lock.<br>

  The PLL simulation model will lose lock when there is a difference between the input and the feedback clocks. This is due to the difficulty in modelling the actual PLL hardware. TN1178 recommends that you do not switch the input clock to the PLL as ...

• 1719 - LatticeECP3: How do I&nbsp;get the Lattice FPGA&nbsp;DCS to switch from an inactive clock to an active one in simulation?

  DCS is a global clock buffer incorporating a smart multiplexer function that takes two independent input clock sources and avoids glitches or runt pulses on the output clock, regardless of where the enable signal is toggled. When selection input is ...