5951 - iCE40UP: If an external clock/oscillator is going to be used, what pins should be used if the intention is to utilize the primary clock routing?

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• 5590 - Clock: How to route internal oscillator clock to the primary clock network in Radiant?

  Description: This FAQ provide the guide to router internal oscillator clock to the primary clock network in Radiant. Solution: The “USE PRIMARY" option in Radiant Device Constraint Editor can be used to force-connect non-direct access ports to a ...

• 2390 - LatticeECP3: Can all Tx PLL clocks of SERDES drive the primary clock routing directly?<br>

  Description: No, only the Tx PLL half/full rate clocks in channel 0 of each SERDES quad may drive the primary clock routing directly. Eight primary clocks(CLK0~CLK7) may be used for LatticeECP3 devices. To drive the primary clock routing directly: ...

• 970 - How do I implement edge clock routing from a Primary IO (PIO) in a LatticeECP2/M device? <BR>

  You need to locate an input buffer in a dedicated site that supports direct access to the edge clock spine. This applies to PIOs that clock special elements like IDDR/ODDR as well as CLKDIV blocks. Typically, you need to specifiy an EDGE preference ...

• 2475 - Why must I use a Primary Clock Input for a clock instead of a general purpose pin?

  Lattice recommends always using Primary Clock (PCLK) inputs for clocks. An exception is when a clock input is routed directly to a single PLL then a dedicated PLL input should be used. If multiple PLLs are using the same input clock then a PCLK Input ...

• 3829 - In an iCE40LP-CM81 device, can an internal oscillator be used as a clock source in the RTL design?

  An internal oscillator can not be used as a clock source in the RTL design. It is only used for the device configuration.