The delay multiplier is a static value for modifying the PLL output clock's duty cycle. The delay multiplier pushes the clock edge by the equation "delay * delay multiplier". The value of a single delay block is in the datasheet page 3-34, sysCLOCK PLL Timing Table, tPA, "Programmable Delay Unit".
Go to Lattice Website -> Products -> FPGA & CPLD -> ECP3 -> Documentation -> Quick References -> Data Sheet
The value of a "Programmable Delay Unit" in the data sheet is a range because the delay blocks in the FPGA have slight variations in the actual measured delay per Programmable Delay Unit over PVT (process, voltage, and temperature). The delay characteristics might be 90ps per delay for one LatticeECP3 and 150ps per delay for a different LatticeECP3. The tPA delay number can not be changed by software as it is not programmable to different delays. However, the user can add multiple delay blocks together by changing the delay multiplier.