1687 - When implementing PCIe designs with Lattice devices that support SERDES, what should be done with the unused channels?

1687 - When implementing PCIe designs with Lattice devices that support SERDES, what should be done with the unused channels?

Single lane PCIe interfaces to root-complex carriers are often created with optional 4-lane PCIe capabilities in mind. Although this provides future capabilities of the system. it can also create unwanted issues. Connecting of the other 3-lanes (as optional) provides a 4-lane PCIe interface to the root-complex, however this requires some on-board options to disable the optional channels since there is no on-chip capabilities to completely disable the optional lanes.
You need to physically break the connection to the other 3-lanes. This needs to be done by opening the connection to the RX(HDIN). This can be accomplished by adding board components such as 0-ohm resistors to open and close the traces.These carefully placed and routed features are required to ensure the root complex of the carrier does not get a valid electrical link detection. If the optional connection is present, this could cause the root to have issues. There is no "programmable" option to do this. This can only be done on the board.