543 - Do Lattice FPGAs support Spread-Spectrum Clocking (SSC)?

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• 1882 - PLL: When the input clock to the LatticeFPGA PLL is a Spread Spectrum Clock (SSC), does the SSC pass through the PLL, or is it filtered by the PLL?

  The PLL passes the SSC input to the output because the SSC modulation frequency is far below the PLL’s bandwidth (2-4 MHz). This answer specifically applies to industrial standard Spread Spectrum Clocking with a modulation rate between 30 kHz and 33 ...

• 7486 - Where can I find the 3D model of Lattice FPGAs?

  Solution: Users can search the 3D Model of Lattice FPGAs at below link. There are open source libraries that may have the 3D Model, PCB Footprints and Symbol files as the packages are standard and widely used. The link: ...

• 2330 - LatticeECP3: Can LatticeECP3 devices support sub-LVDS IO?

  Description: LatticeECP3 devices do not directly support sub-LVDS IO. But LatticeECP3 can support sub-LVDS IO with an external termination circuit. Please refer to Sub-LVDS Signaling Using Lattice Devices (FPGA-TN-02028) Technical Note available on ...

• 2598 - Can Lattice FPGAs use a general purpose I/O to assert it's own PROGRAMN pin?

  Lattice does not recommend using the FPGA's general purpose I/O to assert its own PROGRAMN pin. There is risk the FPGA may not restart after the first attempt to assert the PROGRAMN pin. The PROGRAMN pin can inadvertently be pulled low, which can ...

• 1100 - How can I use the complimentary outputs in Lattice FPGAs? <br>

  Most Lattice FPGA devices provide a complimentary output feature which allows a single ended buffer to provide its compliment on a different pin without using any FPGA logic resources or user routing. To enable this complimentary path the user needs ...