Clocking Network
2645 - ECP3: How does the Clock Data Recovery (CDR) Loss of Lock pin on the LatticeECP3 behave when the reference clock is stopped?
The CDR Lock detection circuit is a digital counter based on the reference clock. If the clock is removed while the CDR is lock, CDR Loss of Lock will continue to indicate lock status (last registered state). If the input to the Receiver is removed, ...
6523 - Certus-NX: Can LVDS IOs be used on banks 6 & 7 and what limitations are there? Are inputs to be LVDS25E or does that just apply to outputs? For inputs, on banks 6 & 7, are the 100 termination resistors available?
Bank 3, 4, and 5 are the High Speed Banks that support True LVDS. For Bank 6 and 7, although pins can operate through differential pair, its speed is limited to LVCMOS (Input and Output) or LVDS25E (output). Single ended termination with programmable ...
6168 - iCE40 UltraPlus: Why there is no GNDPLL pin for the PLL's filter connection?
Due to packaging size limitations of the iCE40 Ultra Plus devices (ex. iCE40UP5K-SG48), GNDPLL does not exist. In such cases, connecting the GND pins to the ground will suffice.
289 - LatticeXP2: How many times can a FLASHBAK be done in the LatticeXP2?
LatticeXP2 offers FlashBak capability, which is a way to store the data in the EBRs to the Flash memory upon user command. This protects the user’s data from being lost when the system is powered off. The CS100F 90nm FLASH process is specified for ...
2003 - LatticeECP3: We are seeing the primary clock delay to multiple IO Logic elements are the same in the LatticeECP3 device, is this correct?
Yes, the primary clock tree to most of the IOLs in the LatticeECP3 is balanced hence you see the delays are almost the same. The only difference you will see is in primary clock tree delays to SERDES pins or IOL pins at the EBR row ends. The primary ...
5715 - ECP5/ECP5-5G: Do we need a tmwc(Additional Wakeup Master Clock after DONE pin is high) at ECP5 (like at ECP3 = 100 - 500 additional clock cycles)? If yes, what value?
ECP3 and ECP5 are different designs, even though there was an effort to make the ECP5 wakeup sequence behavior as same as ECP3 while developing ECP5, there is a structural difference between them. In term of the tMWC (Additional Wakeup Master Clock ...
2521 - Power ManagerII: Where can I find the process technology information for the Power Manager II products?
Solution:Lattice publishes a Product Family Qualification Summary for the Power Manager II products, found on our website at this link: Power Manager Qualification Summary. This document provides details on the qualification process and results for ...
271 - Power Manager II: Are there speed grades for different Power Manager II Devices, such as ispPAC-POWR1220AT8 or ispPAC-POWR1014A?
No, there is only one speed grade for these devices. The clock signal is internal and based off an 8MHz oscillator. The frequency of the internal oscillator ranges from 7.6MHz to 8.4MHz. The 8MHz oscillator then gets divided down to 250kHz for the ...
6498 - XO/ECP: What is the expected GPLL input clock tR and tF requirements for XO2, XO3, ECP3 and ECP5 ?
For XO2, XO3 and ECP3/ECP5 the expected rise/fall time are shown below: Parameter Descriptions Conditions Max (ns) tR Input clock rise time 10% to 90% 1.0 tF Input clock fall time 90% to 10% 1.0
6478 - MachXO5: What means ATB_FORCE and ATB_SENSE?
ATB_Force and ATB_Sense are pins used for monitoring signals in the Manufacturing Block (Block that generate an interface for testing setup of programming flash and electrical characteristics of various transistors). ATB_Force is an INOUT pin that ...
1965 - LatticeECP2/M: What do users need to consider when using the LatticeECP2/M Dynamic Clock Select (DCS)?
Documentation on LatticeECP2/M's DCS is located in page 10-29 of the LatticeECP2/M SysClock PLL/DLL Design and Usage Guide. The link to the Application note(TN1103) can be located here. One of the issues that users will run into when using the DCS is ...
2475 - Why must I use a Primary Clock Input for a clock instead of a general purpose pin?
Lattice recommends always using Primary Clock (PCLK) inputs for clocks. An exception is when a clock input is routed directly to a single PLL then a dedicated PLL input should be used. If multiple PLLs are using the same input clock then a PCLK Input ...
5611 - MachXO3 : How do designer deal with Metastability?
Metastability can occur in a number of asynchronous systems, usually due to the inability to guarantee that the setup time of the flip-flops will be satisfied. In standard synchronous systems where the setup time (and all other timing requirements) ...
1957 - [LatticeECP3] Is there a method to partition a PRIMARY clock network?
Yes, each PRIMARY global clock nets in a LatticeECP3 device can be partitioned into four QUADRANTs. In a LatticeECP3 device, there are a total of 8 PRIMARY global clock nets. If each of them can be partitioned, then it is possible to have up to 32 ...
3740 - ispMACH 4000: What is the difference between "External feedback" and "internal feedback" when calculating Fmax for ispMACH 4000 devices?
When calculating the Fmax , the following two cases are considered 1. Internal feedback 2. External feedback When the signal is fed back through the GRP (global routing pool) without going through an IO pad, it is internal feedback whereas when it is ...
3702 - LatticeECP3: How do user configure MCLK clock in the JESD207 IP Core other than its default frequency(90MHz) ?
Generate new PLL for the MCLK frequency with the same IO ports and same PLL name and replace this newly generated PLL *.v or *.vhd file with the existing one.