6168 - iCE40 UltraPlus: Why there is no GNDPLL pin for the PLL's filter connection?

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• What is the difference between PCLKT and PLLT as dedicated PLL reference clock?

  Both PCLKT and PLLT are legal pin to use as PLL reference clock however there are differences on the clock paths that should take note in designing certain applications. PCLKT Pin: Provides a direct connection to the global and regional clock ...

• 6161 - iCE40 UltraPlus: How utilize Differential Input pairs on an iCE40 device?

  For iCEcube2 compatible devices (LP/HX/LM/Ultra/UltraLite/UltraPlus), the user needs to use the SB_IO primitive and override the IO_STANDARD parameter to SB_LVDS_INPUT as shown in the rudimentary example below: SB_IO SB_IO_inst ( ...

• 538 - LatticeECP2/M / LatticeECP3 / LatticeSC/M: What is the recommended connection for the XRES pin for the LatticeECP2/M, LatticeECP3, and LatticeSC/M devices?

  LatticeECP2/M, LatticeECP3, and LatticeSC/M devices require a single external resistor which is used to create the bias currents for the IO. This resistor is connected between the XRES pin and ground. The device will not initialize and configuration ...

• 7139 - All Nexus: Can user drive PLL dedicated clock input complement pin (GPLL_C) as the single-ended reference clock for the PLL?

  For single-ended clock input to the PLL, user must use the PLL dedicated clock input true pins (GPLL_T). This is similar to the limitation with PCLK_T pins for clock pins. Complement pins must only be used for differential signaling.

• 1882 - PLL: When the input clock to the LatticeFPGA PLL is a Spread Spectrum Clock (SSC), does the SSC pass through the PLL, or is it filtered by the PLL?

  The PLL passes the SSC input to the output because the SSC modulation frequency is far below the PLL’s bandwidth (2-4 MHz). This answer specifically applies to industrial standard Spread Spectrum Clocking with a modulation rate between 30 kHz and 33 ...