6844 - CrossLink-NX ECLK: How can I fit 10 ECLKs on one FPGA?

For each bank, only 4 ECLKs (4 sets of PCLK pins) are available. You may be using more than 4 ECLKs per bank. Carefully, distribute and assign ECLKs to banks 3, 4, and 5 to avoid this issue. You can do this by simply assigning the clock lanes of each DPHY-RX to the PCLK pins of the bank.

Assuming you have 9 DPHY-RX IPs with individual ECLK requirements, a strategy that you could implement is this:

For bank 3, assign the clock lanes of DPHY-RX0, DPHY-RX1, DPHY-RX2, and DPHY-RX3 to the 4 sets of PCLK pins.
For bank 4, assign the clock lanes of DPHY-RX4, DPHY-RX5, DPHY-RX6, and DPHY-RX7 to the 4 sets of PCLK pins.
For bank 5, assign the clock lanes of DPHY-RX8, and DPHY-RX9 to 2 sets of PCLK pins.

Related Articles
6593 - Does Deinterlacer IP available in Crosslink NX?
Deinterlacer IP should support Crosslink NX LIFCL-17. To get the said IP, please refresh IP on Server on the IP Catalog pane of Radiant 3.2SP1, then locate IP > DSP > Deinterlacer. The current version is 1.1.1
6739 - CrossLink-NX: There is described that "VCCM is an internal supply that is derived from VCCAUX and should measure around 1.25 V", What can we check with VCCM?
VCCM is an internal supply, and it is embedded in the silicon which does not have a connection to the pin. The available pins are enumerated in Section 5.2 of FPGA-DS-02049 or Crosslink-NX Family. Hence, we cannot monitor or access VCCM.
3017 - Why cannot I pack two registers with the same clock/clock enable/reset signals into one slice after MAP?
Based on Lattice FPGA architecture, two flip flops in a slice share the same clock/clock enable/reset signals. So the two registers can be packed into one slice if their control signals are same. But sometimes if the reset and/or clock enable signals ...
1719 - LatticeECP3: How do I get the Lattice FPGA DCS to switch from an inactive clock to an active one in simulation?
DCS is a global clock buffer incorporating a smart multiplexer function that takes two independent input clock sources and avoids glitches or runt pulses on the output clock, regardless of where the enable signal is toggled. When selection input is ...
7178 - CertusPro-NX: Why are FPGA I/O lines "zero" by default? How to pull them to 'high' by default?
CertusPro-NX's I/O hardware default is weak pull-down, and it cannot be changed until it is powered up and loaded with bitstream. The only way to get those lines to be 'high' by default is by adding external pull-up resistor on the PCB board.

6844 - CrossLink-NX ECLK: How can I fit 10 ECLKs on one FPGA?

6844 - CrossLink-NX ECLK: How can I fit 10 ECLKs on one FPGA?

Related Articles

6593 - Does Deinterlacer IP available in Crosslink NX?

6739 - CrossLink-NX: There is described that "VCCM is an internal supply that is derived from VCCAUX and should measure around 1.25 V", What can we check with VCCM?

3017 - Why cannot I pack two registers with the same clock/clock enable/reset signals into one slice after MAP?

1719 - LatticeECP3: How do I&nbsp;get the Lattice FPGA&nbsp;DCS to switch from an inactive clock to an active one in simulation?

7178 - CertusPro-NX: Why are FPGA I/O lines "zero" by default? How to pull them to 'high' by default?

1719 - LatticeECP3: How do I get the Lattice FPGA DCS to switch from an inactive clock to an active one in simulation?