6593 - Does Deinterlacer IP available in Crosslink NX?

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• 6739 - CrossLink-NX: There is described that "VCCM is an internal supply that is derived from VCCAUX and should measure around 1.25 V", What can we check with VCCM?

  VCCM is an internal supply, and it is embedded in the silicon which does not have a connection to the pin. The available pins are enumerated in Section 5.2 of FPGA-DS-02049 or Crosslink-NX Family. Hence, we cannot monitor or access VCCM.

• 6844 - CrossLink-NX ECLK: How can I fit 10 ECLKs on one FPGA?

  For each bank, only 4 ECLKs (4 sets of PCLK pins) are available. You may be using more than 4 ECLKs per bank. Carefully, distribute and assign ECLKs to banks 3, 4, and 5 to avoid this issue. You can do this by simply assigning the clock lanes of each ...

• 7150 - IO for Nexus FPGAs: How to set the IO standard to "subLVDS" in GPIO option that is not included in DDR_Generic IP generation?

  The 'subLVDS' option is not available in the IP GUI but user can set "subLVDS" in Device Constraint Editor (DCE) IO_TYPE for proper implementation of subLVDS in this IP.

• 6398 - CertusPro-NX: Does High Performance IO supports hot socketing?

  The Certus-Pro NX HP IOs does not support hot socketing.

• 7312 - Crosslink: How to implement OPENDRAIN on Bi-Directional I/O port in CrossLink device?

  CrossLink I/O does not have OPENDRAIN support for bi-directional pins. This feature is limited by the device hardware itself. However, this product still offers OPENDRAIN support but only limited to output ports only.