PLL
4753 - iCE40 UltraPlus: Error: "The system clock frequency on the PLL output Port A must be between 4 and 133.33 MHz."
For Phase and Delay compensation modes of PLL, the PLL configuration tool of iCECube shows the following error: "The system clock frequency on the PLL output Port A must be between 4 and 133.33 MHz.". However, the data sheet indicates that the max ...
5712 - MachXO3L: Does PLL clock outputs are glitch less when enabled or disabled via ENCLKO*?
The output clocks are glitchless during enabled or disabled event through ENCLKO*.
5898 - iCE40 UltraPlus: With an iCE40 Ultraplus device, how to drive an external pin with a PLL output using Radiant Software?
There are 2 types of PLL outputs that you can use. In Radiant Software, these port outputs are named as "outcore" and "outglobal". After generating the PLL using the IP catalog, you will still need a Top-level module to instantiate the generated PLL. ...
4736 - All Devices: How to improve the jitter value of the PLL clock output?
Follow these recommendations to generate several clock signal outputs with minimum jitter: 1. Use the PLL and the ODDR clocked by the edge clock. 2. Use a clock source with less jitter. 3. Use dedicated clock input routing pins to assign the clock to ...
3678 - PLL: When does the lock of PLL lose?
Description: There could be several reasons for Phase Lock Loop (PLL) losing the lock. 1.If the input clock or feedback signals to the PLL become invalid. 2.If there is Noise in the PLL power supply. 3.If the input clock Period Jitter (tIPJIT) of the ...
793 - PLL: If the PLL loses lock after the LOCK signal has gone high/active, will the LOCK signal go low to indicate that the PLL has lost lock?
Definition: The Lattice FPGA LatticeECP2, LatticeECP2M, LatticeECP3, LatticeSC all have PLL modules. The PLL module has a Lock signal indiating the status of the PLL. For some applications users may use this LOCK signal as a flag or control signal ...
3682 - LatticeECP2/M: What should be the LOCK_SENSITIVITY bit in DQSDLL for DDR interface?
Description: The setting of LOCK_SENSITIVITY bit depends on the operating frequency of DLL: - If the DLL is operated at or above 150 MHz (more sensitive to jitter), set LOCK_SENSITIVITY bit HIGH. For higher frequencies, the system should be more ...
3405 - MachXO2 / IPExpress / PLL : While configuring the PLL in frequency mode, does the IPexpress tool use the fractional-N value?
Solution: The fractional-N value in Ipexpress is supported only in divider mode to generate a fractional output frequency but not in frequency mode.
1753 - LatticeXP2 : How fast can the dynamic phase ports be changed and will this cause glitches?
Phase changes can be made very quickly, up to once every clock cycle. When the dynamic phase inputs of the LatticeXP2 PLL are switched, it is possible that glitches and cycle skips will occur due to the potential timing differences on the dynamic ...
6436 - PLL: What is the recommended accuracy to obtain a stable reference clock as the D-PHY hard core PLL input?
Description:The PLL of the D-PHY hard core will need a stable reference clock as its input. Does Lattice have a recommended accuracy for this reference clock? Solution:There are no specific guidelines as to the recommended accuracy for the reference ...
6897 - Radiant / PLL IP version 1.4.0 and newer: What alternatives can users use for PLL version 1.4.0 reference clock input if they cannot use the onboard oscillator (12 MHz) of the CrossLink-NX Evaluation Board as the clock input?
Users have a couple of options for their design to use the CrossLink-NX evaluation board: 1. Use an external clock from a different clock pin: Instead of using the onboard oscillator, users can connect one of the other PCLK pins as input to the FPGA ...
5253 - iCE40 UltraPlus: Is the Reset signal in PLL generation synchronous or asynchronous in Lattice iCE40?
The Reset signal in PLL generation is asynchronous in Lattice iCE40.
6896 - Why is there a wrong phase difference between the reference and output clocks of PLL for the simulation?
Description: This article explains the wrong phase difference between PLL reference clock and output clock during simulation. Solution: This is a known limitation for Lattice PLL simulation model which depicts a simplified version of the actual PLL ...
4777 - iCEcube2: Placer error saying the PLL instance cannot be placed.
Description: When using PLL in iCEcube2, an error may occur saying it cannot be placed. Solution: The issue is probably due to the "PLL Placement Rules" getting violated. The PLL placement rules are specified in the iCE40 sysCLOCK PLL Design and User ...
4764 - iCE40 Ultra: iCE40 Ultra does not have a GNDPLL pin, is it still recommended to use a filter on VCC_PLL using the normal GND connection?
It is recommended to use filter for the PLL otherwise the operation of the PLL will not be stable. User can use the normal GND connection.
6807 - PLL for MachXO3: Is there a way to use the VCO output directly to the user logic?
VCO frequency cannot be used on the user design. No access point from the VCO output directly to the user logic without passing through the PLL divider. In addition, the maximum clock output frequency of the PLL is also based on the maximum frequency ...
6287 - ICE40 UltraPlus: Does any GBIN input pin can be used to drive the reference clock input to the PLL?
Solution: Yes, Any GBIN pin can be used to drive the reference clock input to the PLL on iCE40. If the PLL instantiated, the the GPLL_IN dual mode cannot be used as input to other pins but could only be used as output pin. With this GPLL_IN pin, is ...
1686 - What is the impact and potential problems when the reference clock input of the PLL in the FPGA is lower than the specification defined in datasheet?
It is common for most of today’s FPGA’s to provide multiple PLLs to support the flexible clock requirements needed for today's complex system design. The PLL has a specific frequency operational range. For example, the LatticeXP2 datasheet indicates ...
6736 - How can I adjust the PLL phase shift in static mode?
These are the equations used to calculate the PLL phase shift. Phase Shift = VCO Phase + Post Divider Phase VCO Phase = 45 * (PHI / (DIV + 1)) Post Divider Phase = 360 * (DEL - DIV) / (DIV + 1) You can find the PHI, DIV, and DEL values on the RTL ...
6703 - MachXO2: What is the wake-up time for PLL, OSC, and Band-gap from the Off (low power state), for all XO2ZE devices up to 2000 LUTs?
The wake-up time for the XO2 after low-power modes is as follows: 100ns for OSC 100us for Bandgap 1-3ms for PLL output activity, 15ms max for PLL lock (same as the datasheet)
1653 - LatticeECP3: Does the PLL (Phase Locked Loop) require a reset after making changes to the Dynamic Phase and Dynamic Duty Cycle Adjustment features?
No, a reset is not required to the PLL after making a dynamic phase or duty cycle adjustment change. These features are not included in the PLL loop and are only on the output of the CLKOS port. The CLKOP port is used as the feedback port on this PLL ...
6668 - MachXO2: What is the wake-up time for PLL, OSC, and Band-gap from the Off (low power state), for all XO2ZE devices up to 2000 LUTs?
The wake-up time for the XO2 after low-power modes is as follows: 100ns for OSC 100us for Bandgap 1-3ms for PLL output activity, 15ms max for PLL lock (same as the datasheet)
7027 - Lattice PLL IP Simulation: slight out-of-phase response even though no phase shift is introduced
Description: The Lattice PLL model is a simplified version of the PLL's features, excluding the loop dynamics that create and control the PLL's internal oscillator. Solution: The phase shift feature refers to the un-phase-shifted output clock and is ...
6213 - All Nexus Devices : Why PLL IP is not able to meet the BW_FACTOR requirement for more complex cases than dividing or multiplying by 2?
For example, reference clock 45MHZ, the output is 11.25 MHz (/4).
Solution : The Fractional-N Divider option should be enabled if the output is a non-integer multiple of the input frequency.
6200 - ECP5/ECP5-5G / PLL - Can ECP5 device supports Spread Spectrum Clock (SSC) generation using generic PLL?
Description: This article clarifies on SSC generation using PLL in ECP5. Solution: ECP5 device does not support Spread Spectrum Clock (SSC) generation using generic PLL. This feature is, however, applicable only by using SerDes PLL.
6192 - All Nexus: How to use the dynamic phase of PLL outputs?
See Section - Dynamic Phase Adjustment of PLL user guide that explains the use of Dynamic Phase for PLL. Dynamic phase adjustment of the PLL output clocks can be done without reconfiguring the FPGA by using the dedicated dynamic phase-shift ports of ...
3899 - iCECube2 / iCE40 / PLL: What is the difference between selecting "PACKAGEPIN" and "General Purpose IO Pad or Core Logic" options during PLL generation?
Solution: If the "Dedicated Clock Pad (single ended)" is selected during the PLL generation, the IO pin connected to the PLL's "PACKAGEPIN" becomes dedicated and hence, the signal coming in from that IO pin can't be used for any other logic design in ...
6506 - PLL: When will the reset of the PLL be released?
If the reset is released before the input clock to the PLL stabilizes (or is input), the PLL does not output the clock and Lock signals.
Definition: When will the reset of the PLL be released? If the reset is released before the input clock to the PLL stabilizes (or is input), the PLL does not output the clock and Lock signals. Solution: Please find section 14.5.3 of FPGA-TN-02095 on ...
2511 - LatticeECP3: Can a LatticeECP3 PLL use a phase-shifted clock output as the feedback clock input?
Description: You can use a phase shifted output clock, such as CLKOS, as the input to the feedback clock. However it is recommended to use a non-phase shifted clock as the feedback clock and adjust the phase as needed on the phase shifted clock ...
3803 - LatticeECP3: How to get the Bandwidth information about the Fabric Phase Lock Loop (PLL) inside the Lattice ECP3 device?
When a PLL Intellectual Property (IP) core is generated for a Lattice ECP3 device, the IP core version 5.4 or above can calculate the Bandwidth of the PLL depending on the input and output frequencies.
6131 - Certus-Nx: Are the outputs of the Nexus platform's sysCLOCK PLL synchronous signals?
Solution: Yes, the outputs of the PLL (e.g. CLKOP, CLKOS, CLKOS2, etc.) are synchronous signals. But you can introduce dissimilar phase shifts to the outputs, either through static or dynamic mode phase adjustment which is available on the Nexus ...
2491 - Is the PLL Lock time, Tlock, measured from power ramp up?
The lock time of the PLL is not gated to power ramp up, it is dependent on the reset signal. After the FPGA is finished configuring, a global reset signal (GSR) is asserted to the chip prior to waking up and operating. PLL lock time, Tlock, is ...
1958 - [LatticeECP3] How do I find the locations of a preferred PLL and its dedicated clock input pin in a LatticeECP3 device?
In a LatticeECP3 device each dedicated clock input pin is paired to specific PLL. This pairing occurs in a form of a dedicated connection between the clock input pin to that PLL. If a user want to use a PLL directly from a clock input pin, he or she ...
2469 - LatticeECP3: Why does the PLL simulation model act differently than hardware?
A PLL is mainly an analog circuit. Because of this, the PLL simulation model cannot operate in the same way as the hardware operates. The PLL simulation model also focuses on balancing a reasonable simulation time with actual hardware results. For ...