3899 - iCECube2 / iCE40 / PLL: What is the difference between selecting "PACKAGEPIN" and "General Purpose IO Pad or Core Logic" options during PLL generation?

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• 5733 - iCE40 Ultra/UltraLite: Can the 48 MHz HFOSC be used as a reference for the internal PLL using iCEcube2 Software?

  Yes, the internal oscillator can be used as a clock source for the PLL. There are specific primitives for this (SB_PLL40_CORE and SB_PLL40_CORE), which will automatically be instantiated when we use the included PLL module generator from iCEcube2 ...

• 6200 - ECP5/ECP5-5G / PLL - Can ECP5 device supports Spread Spectrum Clock (SSC) generation using generic PLL?

  Description: This article clarifies on SSC generation using PLL in ECP5. Solution: ECP5 device does not support Spread Spectrum Clock (SSC) generation using generic PLL. This feature is, however, applicable only by using SerDes PLL.

• 5253 - iCE40 UltraPlus: Is the Reset signal in PLL generation synchronous or asynchronous in Lattice iCE40?

  The Reset signal in PLL generation is asynchronous in Lattice iCE40.

• 6506 - PLL: When will the reset of the PLL be released? If the reset is released before the input clock to the PLL stabilizes (or is input), the PLL does not output the clock and Lock signals.

  Definition: When will the reset of the PLL be released? If the reset is released before the input clock to the PLL stabilizes (or is input), the PLL does not output the clock and Lock signals. Solution: Please find section 14.5.3 of FPGA-TN-02095 on ...

• 6807 - PLL for MachXO3: Is there a way to use the VCO output directly to the user logic?

  VCO frequency cannot be used on the user design. No access point from the VCO output directly to the user logic without passing through the PLL divider. In addition, the maximum clock output frequency of the PLL is also based on the maximum frequency ...