6200 - ECP5/ECP5-5G / PLL - Can ECP5 device supports Spread Spectrum Clock (SSC) generation using generic PLL?

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• 1332 - Can LatticeECP3 FPGA PLLs accept Spread Spectrum Input clock?

  PLLs are designed to track input clocks that have a low frequency drift. The LatticeECP3 FPGA PLLs can accept a spread spectrum clock modulated with low frequency (33KHz). The PLLs while capable of receiving spread spectrum clocks, do not generate ...

• 1958 - [LatticeECP3] How do I find the locations of a preferred PLL and its dedicated clock input pin in a LatticeECP3 device?

  In a LatticeECP3 device each dedicated clock input pin is paired to specific PLL. This pairing occurs in a form of a dedicated connection between the clock input pin to that PLL. If a user want to use a PLL directly from a clock input pin, he or she ...

• 3899 - iCECube2 / iCE40 / PLL: What is the difference between selecting "PACKAGEPIN" and "General Purpose IO Pad or Core Logic" options during PLL generation?

  Solution: If the "Dedicated Clock Pad (single ended)" is selected during the PLL generation, the IO pin connected to the PLL's "PACKAGEPIN" becomes dedicated and hence, the signal coming in from that IO pin can't be used for any other logic design in ...

• 4736 - All Devices: How to improve the jitter value of the PLL clock output?

  Follow these recommendations to generate several clock signal outputs with minimum jitter: 1. Use the PLL and the ODDR clocked by the edge clock. 2. Use a clock source with less jitter. 3. Use dedicated clock input routing pins to assign the clock to ...

• 793 - PLL: If the PLL loses lock after the LOCK signal has gone high/active, will the LOCK signal go low to indicate that the PLL has lost lock?

  Definition: The Lattice FPGA LatticeECP2, LatticeECP2M, LatticeECP3, LatticeSC all have PLL modules. The PLL module has a Lock signal indiating the status of the PLL. For some applications users may use this LOCK signal as a flag or control signal ...