How to access the Nexus PLL configuration space register via APB2LMMI?

One of the most common points of confusion stems from the updated address mapping in PLL version 1.9.0. Previously, the APB interface used a different width and offset scheme for accessing PLL registers. However, with the release of this version, the interface has been upgraded to support 32-bit address and data width across the APB2LMMI bus. This change improves data throughput and aligns with modern bus standards, but it also requires developers to adjust their register access logic accordingly.

The key shift is that the LMMI Offset addresses are now mapped to bits 2 through 8 of the 32-bit APB address. This means that simply using the old offset values without reinterpreting their position in the 32-bit address space will result in incorrect register reads or no response at all.

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