6441 - PLL for Nexus FPGAs: How to dynamically change the PLL output frequency?

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• 3815 - <div>For the MachXO2 device,&nbsp;how&nbsp;to&nbsp;make dynamic changes to the PLL&nbsp;output frequency?&nbsp;Can the PLL be dynamically controlled by changing the registers?&nbsp;Is a reset required for the PLL after changing&nbsp;these registers

  The MachXO2 device has an option to make dynamic update to the PLL. Registers 0 through 11 are user accessible registers. The remaining registers are reserved for Lattice use or read-only access, and the user cannot write these. For more information, ...

• 4753 - iCE40 UltraPlus: Error: "The system clock frequency on the PLL output Port A must be between 4 and 133.33 MHz."

  For Phase and Delay compensation modes of PLL, the PLL configuration tool of iCECube shows the following error: "The system clock frequency on the PLL output Port A must be between 4 and 133.33 MHz.". However, the data sheet indicates that the max ...

• 1155 - Why won't the second PLL in a cascaded PLL design achieve lock during simulation?

  My design uses 2 PLLs that are cascaded; i.e the output of the 1st PLL is the input of the 2nd PLL. The 1st PLL functions fine in simulations but the 2nd PLL will not achieve lock and the output frequency is not correct. The input frequency of the ...

• 6807 - PLL for MachXO3: Is there a way to use the VCO output directly to the user logic?

  VCO frequency cannot be used on the user design. No access point from the VCO output directly to the user logic without passing through the PLL divider. In addition, the maximum clock output frequency of the PLL is also based on the maximum frequency ...

• 6213 - All Nexus Devices : Why PLL IP is not able to meet the BW_FACTOR requirement for more complex cases than dividing or multiplying by 2? For example, reference clock 45MHZ, the output is 11.25 MHz (/4).

  Solution : The Fractional-N Divider option should be enabled if the output is a non-integer multiple of the input frequency.