4753 - iCE40 UltraPlus: Error: "The system clock frequency on the PLL output Port A must be between 4 and 133.33 MHz."

4753 - iCE40 UltraPlus: Error: "The system clock frequency on the PLL output Port A must be between 4 and 133.33 MHz."

For Phase and Delay compensation modes of PLL, the PLL configuration tool of iCECube shows the following error: "The system clock frequency on the PLL output Port A must be between 4 and 133.33 MHz.". However, the data sheet indicates that the max fout can be 275 MHz. The PLL output for phase and delay compensation modes will go to max 133.33 MHz and that is the reason you are getting this message. Whereas for no-compensation mode it will go to the max value specified in the data sheet.