5898 - iCE40 UltraPlus: With an iCE40 Ultraplus device, how to drive an external pin with a PLL output using Radiant Software?

• Related Articles

• 6287 - ICE40 UltraPlus: Does any GBIN input pin can be used to drive the reference clock input to the PLL?

  Solution: Yes, Any GBIN pin can be used to drive the reference clock input to the PLL on iCE40. If the PLL instantiated, the the GPLL_IN dual mode cannot be used as input to other pins but could only be used as output pin. With this GPLL_IN pin, is ...

• 6430 - CertusPro-NX / ADC: Why is a PLL used to drive the ADC adc_clk_i pin and not directly driven by an oscillator output?

  Description:This article explains the reason ADC clock-in cannot be driven using an oscillator output in CertusPro-NX. Solution:In CertusPro-NX., the ADC clock input is hard-wired on the fabric to the 4th secondary output (CLKOS4) of the Lower Right ...

• 1958 - [LatticeECP3] How do I find the locations of a preferred PLL and its dedicated clock input pin in a LatticeECP3 device?

  In a LatticeECP3 device each dedicated clock input pin is paired to specific PLL. This pairing occurs in a form of a dedicated connection between the clock input pin to that PLL. If a user want to use a PLL directly from a clock input pin, he or she ...

• 6200 - ECP5/ECP5-5G / PLL - Can ECP5 device supports Spread Spectrum Clock (SSC) generation using generic PLL?

  Description: This article clarifies on SSC generation using PLL in ECP5. Solution: ECP5 device does not support Spread Spectrum Clock (SSC) generation using generic PLL. This feature is, however, applicable only by using SerDes PLL.

• 4736 - All Devices: How to improve the jitter value of the PLL clock output?

  Follow these recommendations to generate several clock signal outputs with minimum jitter: 1. Use the PLL and the ODDR clocked by the edge clock. 2. Use a clock source with less jitter. 3. Use dedicated clock input routing pins to assign the clock to ...