6897 - Radiant / PLL IP version 1.4.0 and newer: What alternatives can users use for PLL version 1.4.0 reference clock input if they cannot use the onboard oscillator (12 MHz) of the CrossLink-NX Evaluation Board as the clock input?

Users have a couple of options for their design to use the CrossLink-NX evaluation board:

1. Use an external clock from a different clock pin: Instead of using the onboard oscillator, users can connect one of the other PCLK pins as input to the FPGA PLL. But this is assuming that users have an off-board external clock generator.

2. Use the internal FPGA oscillator as input to the PLL: Users can also use the internal FPGA oscillator as the input to the PLL. See that the oscillator can have an 18 MHz output frequency or higher that can be used as an input to the PLL.

3. Use the FPGA oscillator directly on the design: The user can also remove the PLL out of the design and use the oscillator of the FPGA directly. Take note that you can adjust the frequency of the oscillator to some values only. Refer to the oscillator-related documentation for more details.

4. Use the old PLL version: If users still have the old project, you can open it on Radiant 2022.1 SP1 but do not regenerate the PLL IP to the new version. Users can still generate the bitstream and use the older version of the PLL (lower than version 1.4.0).

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