6897 - Radiant / PLL IP version 1.4.0 and newer: What alternatives can users use for PLL version 1.4.0 reference clock input if they cannot use the onboard oscillator (12 MHz) of the CrossLink-NX Evaluation Board as the clock input?

Users have a couple of options for their design to use the CrossLink-NX evaluation board:
1. Use an external clock from a different clock pin: Instead of using the onboard oscillator, users can connect one of the other PCLK pins as input to the FPGA PLL. But this is assuming that users have an off-board external clock generator.

2. Use the internal FPGA oscillator as input to the PLL: Users can also use the internal FPGA oscillator as the input to the PLL. See that the oscillator can have an 18 MHz output frequency or higher that can be used as an input to the PLL.

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6897 - Radiant / PLL IP version 1.4.0 and newer: What alternatives can users use for PLL version 1.4.0 reference clock input if they cannot use the onboard oscillator (12 MHz) of the CrossLink-NX Evaluation Board as the clock input?

6897 - Radiant / PLL IP version 1.4.0 and newer: What alternatives can users use for PLL version 1.4.0 reference clock input if they cannot use the onboard oscillator (12 MHz) of the CrossLink-NX Evaluation Board as the clock input?

Related Articles

6436 - PLL: What is the recommended accuracy to obtain a stable reference clock as the D-PHY hard core PLL input?

6287 - ICE40 UltraPlus: Does any GBIN input pin can be used to drive the reference clock input to the PLL?

6274 - CrossLink-NX: How to use the GDDR_SYNC Soft IP?

6430 - CertusPro-NX / ADC: Why is a PLL used to drive the ADC adc_clk_i pin and not directly driven by an oscillator output?

2511 - LatticeECP3: Can a LatticeECP3 PLL use a phase-shifted clock output as the feedback clock input?