6274 - CrossLink-NX: How to use the GDDR_SYNC Soft IP?

Please refer to Section 9. Soft IP Modules of the FPGA-TN-02097 (CrossLink-NX High-Speed I/O Interface Technical Note).

The said Soft IPs are used in Generic DDR IP depending on the Interface as seen in Table 9.2.Soft IP Used in Each Interface.

After generating the ddr_generic module, the user should be able to see the corresponding modules. If the user needs ports such as stop and ddr_reset, they should extract these. Specifically, if the user needs to instantiate those pins, they should do so up to the top-level module, where the input and output ports are assigned to the device pins.

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6274 - CrossLink-NX: How to use the GDDR_SYNC Soft IP?

6274 - CrossLink-NX: How to use the GDDR_SYNC Soft IP?

Related Articles

6897 - Radiant / PLL IP version 1.4.0 and newer: What alternatives can users use for PLL version 1.4.0 reference clock input if they cannot use the onboard oscillator (12 MHz) of the CrossLink-NX Evaluation Board as the clock input?

5568 - Diamond/MachXO3: How to use the Lattice primitives in this device family?

6482 - CrossLink-NX: Does LIFCL-40/LIFCL-17 CSFBGA121 has external VREF pin for ADC?

6510 - CrossLink-NX: What is the accuracy of ADC Internal Reference Voltage?

5897 - CrossLink: Is it possible that the MIPIDPHYA IP core be modified such that these 4 parameters namely CO, CM, CN, TX_FREG_TGT become 4 input ports that can be controlled at runtime?