6436 - PLL: What is the recommended accuracy to obtain a stable reference clock as the D-PHY hard core PLL input?

Description:The PLL of the D-PHY hard core will need a stable reference clock as its input. Does Lattice have a recommended accuracy for this reference clock?

Solution:There are no specific guidelines as to the recommended accuracy for the reference clock. Our suggestion is to use an external clock instead of the device clock since it is more accurate.
For the case of CrossLink's Masterlink board, it uses an oscillator clock device with 50PPM accuracy and it is working fine. Hence, 50PPM accuracy would be good enough for this case.

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6436 - PLL: What is the recommended accuracy to obtain a stable reference clock as the D-PHY hard core PLL input?

6436 - PLL: What is the recommended accuracy to obtain a stable reference clock as the D-PHY hard core PLL input?

Related Articles

6287 - ICE40 UltraPlus: Does any GBIN input pin can be used to drive the reference clock input to the PLL?

1686 - What&nbsp;is&nbsp;the impact and potential problems&nbsp;when&nbsp;the reference clock input of the PLL in the FPGA is lower than the specification defined in datasheet? &nbsp;

2511 - LatticeECP3: Can a LatticeECP3 PLL use a phase-shifted clock output as the feedback clock input?

6506 - PLL: When will the reset of the PLL be released? If the reset is released before the input clock to the PLL stabilizes (or is input), the PLL does not output the clock and Lock signals.

1958 - [LatticeECP3] How do I find the locations of a preferred PLL and its dedicated clock input pin in a LatticeECP3 device?

1686 - What is the impact and potential problems when the reference clock input of the PLL in the FPGA is lower than the specification defined in datasheet?