2511 - LatticeECP3: Can a LatticeECP3 PLL use a phase-shifted clock output as the feedback clock input?

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• 6896 - Why is there a wrong phase difference between the reference and output clocks of PLL for the simulation?

  Description: This article explains the wrong phase difference between PLL reference clock and output clock during simulation. Solution: This is a known limitation for Lattice PLL simulation model which depicts a simplified version of the actual PLL ...

• 7027 - Lattice PLL IP Simulation: slight out-of-phase response even though no phase shift is introduced

  Description: The Lattice PLL model is a simplified version of the PLL's features, excluding the loop dynamics that create and control the PLL's internal oscillator. Solution: The phase shift feature refers to the un-phase-shifted output clock and is ...

• 6192 - All Nexus: How to use the dynamic phase of PLL outputs?

  See Section - Dynamic Phase Adjustment of PLL user guide that explains the use of Dynamic Phase for PLL. Dynamic phase adjustment of the PLL output clocks can be done without reconfiguring the FPGA by using the dedicated dynamic phase-shift ports of ...

• 6506 - PLL: When will the reset of the PLL be released? If the reset is released before the input clock to the PLL stabilizes (or is input), the PLL does not output the clock and Lock signals.

  Definition: When will the reset of the PLL be released? If the reset is released before the input clock to the PLL stabilizes (or is input), the PLL does not output the clock and Lock signals. Solution: Please find section 14.5.3 of FPGA-TN-02095 on ...

• 6287 - ICE40 UltraPlus: Does any GBIN input pin can be used to drive the reference clock input to the PLL?

  Solution: Yes, Any GBIN pin can be used to drive the reference clock input to the PLL on iCE40. If the PLL instantiated, the the GPLL_IN dual mode cannot be used as input to other pins but could only be used as output pin. With this GPLL_IN pin, is ...