6896 - Why is there a wrong phase difference between the reference and output clocks of PLL for the simulation?

• Related Articles

• 2511 - LatticeECP3: Can a LatticeECP3 PLL use a phase-shifted clock output as the feedback clock input?

  Description: You can use a phase shifted output clock, such as CLKOS, as the input to the feedback clock. However it is recommended to use a non-phase shifted clock as the feedback clock and adjust the phase as needed on the phase shifted clock ...

• 7027 - Lattice PLL IP Simulation: slight out-of-phase response even though no phase shift is introduced

  Description: The Lattice PLL model is a simplified version of the PLL's features, excluding the loop dynamics that create and control the PLL's internal oscillator. Solution: The phase shift feature refers to the un-phase-shifted output clock and is ...

• 6736 - How can I adjust the PLL phase shift in static mode?

  These are the equations used to calculate the PLL phase shift. Phase Shift = VCO Phase + Post Divider Phase VCO Phase = 45 * (PHI / (DIV + 1)) Post Divider Phase = 360 * (DEL - DIV) / (DIV + 1) You can find the PHI, DIV, and DEL values on the RTL ...

• 6192 - All Nexus: How to use the dynamic phase of PLL outputs?

  See Section - Dynamic Phase Adjustment of PLL user guide that explains the use of Dynamic Phase for PLL. Dynamic phase adjustment of the PLL output clocks can be done without reconfiguring the FPGA by using the dedicated dynamic phase-shift ports of ...

• 2469 - LatticeECP3: Why does the PLL simulation model act differently than hardware?

  A PLL is mainly an analog circuit. Because of this, the PLL simulation model cannot operate in the same way as the hardware operates. The PLL simulation model also focuses on balancing a reasonable simulation time with actual hardware results. For ...