6736 - How can I adjust the PLL phase shift in static mode?

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• 7027 - Lattice PLL IP Simulation: slight out-of-phase response even though no phase shift is introduced

  Description: The Lattice PLL model is a simplified version of the PLL's features, excluding the loop dynamics that create and control the PLL's internal oscillator. Solution: The phase shift feature refers to the un-phase-shifted output clock and is ...

• 2511 - LatticeECP3: Can a LatticeECP3 PLL use a phase-shifted clock output as the feedback clock input?

  Description: You can use a phase shifted output clock, such as CLKOS, as the input to the feedback clock. However it is recommended to use a non-phase shifted clock as the feedback clock and adjust the phase as needed on the phase shifted clock ...

• 6192 - All Nexus: How to use the dynamic phase of PLL outputs?

  See Section - Dynamic Phase Adjustment of PLL user guide that explains the use of Dynamic Phase for PLL. Dynamic phase adjustment of the PLL output clocks can be done without reconfiguring the FPGA by using the dedicated dynamic phase-shift ports of ...

• 6896 - Why is there a wrong phase difference between the reference and output clocks of PLL for the simulation?

  Description: This article explains the wrong phase difference between PLL reference clock and output clock during simulation. Solution: This is a known limitation for Lattice PLL simulation model which depicts a simplified version of the actual PLL ...

• 6131 - Certus-Nx: Are the outputs of the Nexus platform's sysCLOCK PLL synchronous signals?

  Solution: Yes, the outputs of the PLL (e.g. CLKOP, CLKOS, CLKOS2, etc.) are synchronous signals. But you can introduce dissimilar phase shifts to the outputs, either through static or dynamic mode phase adjustment which is available on the Nexus ...