6192 - All Nexus: How to use the dynamic phase of PLL outputs?
See Section - Dynamic Phase Adjustment of PLL user guide that explains the use of Dynamic Phase for PLL.
Dynamic phase adjustment of the PLL output clocks can be done without reconfiguring the FPGA by using the dedicated dynamic phase-shift ports of the PLL.
All six output clocks, CLKOP, CLKOS, CLKOS2, CLKOS3, CLKOS4, and CLKOS5 have the dynamic phase adjustment feature but only one output clock can be adjusted at a time. Table 14.3 shows the output clock selection settings available for the PHASESEL[2:0] signal. The PHASESEL signal must be stable for 5 ns before the PHASESTEP or PHASELOADREG signals are pulsed.
The selected output clock phase is either advanced or delayed depending upon the value of the PHASEDIR port. Table 14.4 shows the PHASEDIR settings available. The PHASEDIR signal must be stable for 5 ns before the PHASESTEP or PHASELOADREG signals are pulsed.
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