6131 - Certus-Nx: Are the outputs of the Nexus platform's sysCLOCK PLL synchronous signals?

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• 6192 - All Nexus: How to use the dynamic phase of PLL outputs?

  See Section - Dynamic Phase Adjustment of PLL user guide that explains the use of Dynamic Phase for PLL. Dynamic phase adjustment of the PLL output clocks can be done without reconfiguring the FPGA by using the dedicated dynamic phase-shift ports of ...

• 6506 - PLL: When will the reset of the PLL be released? If the reset is released before the input clock to the PLL stabilizes (or is input), the PLL does not output the clock and Lock signals.

  Definition: When will the reset of the PLL be released? If the reset is released before the input clock to the PLL stabilizes (or is input), the PLL does not output the clock and Lock signals. Solution: Please find section 14.5.3 of FPGA-TN-02095 on ...

• 5253 - iCE40 UltraPlus: Is the Reset signal in PLL generation synchronous or asynchronous in Lattice iCE40?

  The Reset signal in PLL generation is asynchronous in Lattice iCE40.

• 1155 - Why won't the second PLL in a cascaded PLL design achieve lock during simulation?

  My design uses 2 PLLs that are cascaded; i.e the output of the 1st PLL is the input of the 2nd PLL. The 1st PLL functions fine in simulations but the 2nd PLL will not achieve lock and the output frequency is not correct. The input frequency of the ...

• 6430 - CertusPro-NX / ADC: Why is a PLL used to drive the ADC adc_clk_i pin and not directly driven by an oscillator output?

  Description:This article explains the reason ADC clock-in cannot be driven using an oscillator output in CertusPro-NX. Solution:In CertusPro-NX., the ADC clock input is hard-wired on the fabric to the 4th secondary output (CLKOS4) of the Lower Right ...