7027 - Lattice PLL IP Simulation: slight out-of-phase response even though no phase shift is introduced

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• 6896 - Why is there a wrong phase difference between the reference and output clocks of PLL for the simulation?

  Description: This article explains the wrong phase difference between PLL reference clock and output clock during simulation. Solution: This is a known limitation for Lattice PLL simulation model which depicts a simplified version of the actual PLL ...

• 6736 - How can I adjust the PLL phase shift in static mode?

  These are the equations used to calculate the PLL phase shift. Phase Shift = VCO Phase + Post Divider Phase VCO Phase = 45 * (PHI / (DIV + 1)) Post Divider Phase = 360 * (DEL - DIV) / (DIV + 1) You can find the PHI, DIV, and DEL values on the RTL ...

• 2511 - LatticeECP3: Can a LatticeECP3 PLL use a phase-shifted clock output as the feedback clock input?

  Description: You can use a phase shifted output clock, such as CLKOS, as the input to the feedback clock. However it is recommended to use a non-phase shifted clock as the feedback clock and adjust the phase as needed on the phase shifted clock ...

• 6192 - All Nexus: How to use the dynamic phase of PLL outputs?

  See Section - Dynamic Phase Adjustment of PLL user guide that explains the use of Dynamic Phase for PLL. Dynamic phase adjustment of the PLL output clocks can be done without reconfiguring the FPGA by using the dedicated dynamic phase-shift ports of ...

• 3803 - LatticeECP3: How to get the Bandwidth information about the Fabric Phase Lock Loop (PLL) inside the Lattice ECP3 device?

  When a PLL Intellectual Property (IP) core is generated for a Lattice ECP3 device, the IP core version 5.4 or above can calculate the Bandwidth of the PLL depending on the input and output frequencies.