6506 - PLL: When will the reset of the PLL be released?
If the reset is released before the input clock to the PLL stabilizes (or is input), the PLL does not output the clock and Lock signals.
Definition:
When will the reset of the PLL be released?
If the reset is released before the input clock to the PLL stabilizes (or is input), the PLL does not output the clock and Lock signals.
Solution:
Please find section 14.5.3 of FPGA-TN-02095 on the RST input as well as the timing diagram in Figure 14.9.
At power-up, an internal power-up reset signal from the configuration block resets the PLL. Additionally, an active high, asynchronous, user-controlled reset port can be optionally added to the PLL. The RST signal can be driven by an internally generated reset function or by an I/O pin. This RST signal resets the PLL core (VCO, phase detector, and charge pump) and the output dividers which causes the outputs to be logic 0. In bypass mode, the output does not reset.After the RST signal is deasserted, the PLL starts the lock-in process and takes tLOCK time, about 16 ms, to complete. Figure 14.9 shows the timing diagram of the RST input. The RST signal is active high. The RST signal is optional. Trst = 1 ms reset pulse width, Trstrec = 1 ns time after a reset before the divider output starts counting again.
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