2491 - Is the PLL Lock time, Tlock, measured from power ramp up?
The lock time of the PLL is not gated to power ramp up, it is dependent on the reset signal. After the FPGA is finished configuring, a global reset signal (GSR) is asserted to the chip prior to waking up and operating. PLL lock time, Tlock, is specified from the time the GSR is released to the time of lock, as long as the input clock is consistent.
Related Articles
6506 - PLL: When will the reset of the PLL be released?
If the reset is released before the input clock to the PLL stabilizes (or is input), the PLL does not output the clock and Lock signals.
Definition: When will the reset of the PLL be released? If the reset is released before the input clock to the PLL stabilizes (or is input), the PLL does not output the clock and Lock signals. Solution: Please find section 14.5.3 of FPGA-TN-02095 on ...
6703 - MachXO2: What is the wake-up time for PLL, OSC, and Band-gap from the Off (low power state), for all XO2ZE devices up to 2000 LUTs?
The wake-up time for the XO2 after low-power modes is as follows: 100ns for OSC 100us for Bandgap 1-3ms for PLL output activity, 15ms max for PLL lock (same as the datasheet)
6668 - MachXO2: What is the wake-up time for PLL, OSC, and Band-gap from the Off (low power state), for all XO2ZE devices up to 2000 LUTs?
The wake-up time for the XO2 after low-power modes is as follows: 100ns for OSC 100us for Bandgap 1-3ms for PLL output activity, 15ms max for PLL lock (same as the datasheet)
3678 - <span id="lf104285">PLL: When does the lock of PLL lose?</span>
Description: There could be several reasons for Phase Lock Loop (PLL) losing the lock. 1.If the input clock or feedback signals to the PLL become invalid. 2.If there is Noise in the PLL power supply. 3.If the input clock Period Jitter (tIPJIT) of the ...
793 - PLL: If the PLL loses lock after the LOCK signal has gone high/active, will the LOCK signal go low to indicate that the PLL has lost lock?
Definition: The Lattice FPGA LatticeECP2, LatticeECP2M, LatticeECP3, LatticeSC all have PLL modules. The PLL module has a Lock signal indiating the status of the PLL. For some applications users may use this LOCK signal as a flag or control signal ...