2491 - Is the PLL Lock time, Tlock, measured from power ramp up?
The lock time of the PLL is not gated to power ramp up, it is dependent on the reset signal. After the FPGA is finished configuring, a global reset signal (GSR) is asserted to the chip prior to waking up and operating. PLL lock time, Tlock, is specified from the time the GSR is released to the time of lock, as long as the input clock is consistent.
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Which power supplies are used by the PLL in Avant?
The VCCA_PLL* and VCC are the power supplies connected to the PLL power rails.
6506 - PLL: When will the reset of the PLL be released?
If the reset is released before the input clock to the PLL stabilizes (or is input), the PLL does not output the clock and Lock signals.
Definition: When will the reset of the PLL be released? If the reset is released before the input clock to the PLL stabilizes (or is input), the PLL does not output the clock and Lock signals. Solution: Please find section 14.5.3 of FPGA-TN-02095 on ...
3678 - PLL: When does the lock of PLL lose?
Description: There could be several reasons for Phase Lock Loop (PLL) losing the lock. 1.If the input clock or feedback signals to the PLL become invalid. 2.If there is Noise in the PLL power supply. 3.If the input clock Period Jitter (tIPJIT) of the ...
6703 - MachXO2: What is the wake-up time for PLL, OSC, and Band-gap from the Off (low power state), for all XO2ZE devices up to 2000 LUTs?
The wake-up time for the XO2 after low-power modes is as follows: 100ns for OSC 100us for Bandgap 1-3ms for PLL output activity, 15ms max for PLL lock (same as the datasheet)
6668 - MachXO2: What is the wake-up time for PLL, OSC, and Band-gap from the Off (low power state), for all XO2ZE devices up to 2000 LUTs?
The wake-up time for the XO2 after low-power modes is as follows: 100ns for OSC 100us for Bandgap 1-3ms for PLL output activity, 15ms max for PLL lock (same as the datasheet)