6703 - MachXO2: What is the wake-up time for PLL, OSC, and Band-gap from the Off (low power state), for all XO2ZE devices up to 2000 LUTs?

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• 6668 - MachXO2: What is the wake-up time for PLL, OSC, and Band-gap from the Off (low power state), for all XO2ZE devices up to 2000 LUTs?

  The wake-up time for the XO2 after low-power modes is as follows: 100ns for OSC 100us for Bandgap 1-3ms for PLL output activity, 15ms max for PLL lock (same as the datasheet)

• Which power supplies are used by the PLL in Avant?

  The VCCA_PLL* and VCC are the power supplies connected to the PLL power rails.

• 2491 - Is the PLL Lock time, Tlock, measured from power ramp up?

  The lock time of the PLL is not gated to power ramp up, it is dependent on the reset signal. After the FPGA is finished configuring, a global reset signal (GSR) is asserted to the chip prior to waking up and operating. PLL lock time, Tlock, is ...

• 1154 - Will the PLL in my FPGA work using a 25MHz input clock with a duty cycle of 33%(low) or 66%(high)?

  The PLLs in most Lattice FPGAs should operate correctly using a 25 MHz input clock with duty cycles of 33%(low) or 66%(high). Check the data sheet for the specific FPGA you are using to determine the operating limits of the PLL. Look in the data ...

• How to access the Nexus PLL configuration space register via APB2LMMI?

  One of the most common points of confusion stems from the updated address mapping in PLL version 1.9.0. Previously, the APB interface used a different width and offset scheme for accessing PLL registers. However, with the release of this version, the ...