1154 - Will the PLL in my FPGA work using a 25MHz input clock with a duty cycle of 33%(low) or 66%(high)?

The PLLs in most Lattice FPGAs should operate correctly using a 25 MHz input clock with duty cycles of 33%(low) or 66%(high).

Check the data sheet for the specific FPGA you are using to determine the operating limits of the PLL. Look in the data sheet under the "DC and Switching Characteristics" section for the PLL operating limits. The input clock frequency must be within the listed input frequency range for the PLL.

The duty cycle is not listed in the data sheet explicitly. The input clock cannot exceed the minimum clock high or low time as given in the data sheet (0.5 ns is a typical value). Multiply the duty cycle by the clock period to determine the high and low times for the input clock.

Using the 25 MHz (40 ns period) input clock example, a 33% low time is 13.2 ns (40 * 0.33) which provides plenty of margin over the data sheet specification of 0.5 ns.

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1154 - <p>Will the PLL in my FPGA work using a 25MHz input clock with a duty cycle of 33%(low) or 66%(high)?<br></p>

1154 - <p>Will the PLL in my FPGA work using a 25MHz input clock with a duty cycle of 33%(low) or 66%(high)?<br></p>

Related Articles

793 - <p>PLL: If the PLL loses lock after the LOCK signal has gone high/active, will the LOCK signal go low to indicate that the PLL has lost lock? </p>

6506 - PLL: When will the reset of the PLL be released? If the reset is released before the input clock to the PLL stabilizes (or is input), the PLL does not output the clock and Lock signals.

6897 - Radiant / PLL IP version 1.4.0 and newer: What alternatives can users use for PLL version 1.4.0 reference clock input if they cannot use the onboard oscillator (12 MHz) of the CrossLink-NX Evaluation Board as the clock input?

1653 - LatticeECP3: Does the PLL (Phase Locked Loop) require a reset after making changes to the Dynamic Phase and Dynamic Duty Cycle Adjustment features?

1686 - What is the impact and potential problems when the reference clock input of the PLL in the FPGA is lower than the specification defined in datasheet?

1154 - <p>Will the PLL in my FPGA work using a 25MHz input clock with a duty cycle of 33%(low) or 66%(high)?<br></p>

1154 - <p>Will the PLL in my FPGA work using a 25MHz input clock with a duty cycle of 33%(low) or 66%(high)?<br></p>

Related Articles

793 - <p>PLL: If the PLL loses lock after the LOCK signal has gone high/active, will the LOCK signal go low to indicate that the PLL has lost lock? </p>

6506 - PLL: When will the reset of the PLL be released? If the reset is released before the input clock to the PLL stabilizes (or is input), the PLL does not output the clock and Lock signals.

6897 - Radiant / PLL IP version 1.4.0 and newer: What alternatives can users use for PLL version 1.4.0 reference clock input if they cannot use the onboard oscillator (12 MHz) of the CrossLink-NX Evaluation Board as the clock input?

1653 - LatticeECP3: Does the PLL (Phase Locked Loop) require a reset after making changes to the&nbsp;Dynamic Phase and Dynamic Duty Cycle Adjustment features?

1686 - What&nbsp;is&nbsp;the impact and potential problems&nbsp;when&nbsp;the reference clock input of the PLL in the FPGA is lower than the specification defined in datasheet? &nbsp;

1653 - LatticeECP3: Does the PLL (Phase Locked Loop) require a reset after making changes to the Dynamic Phase and Dynamic Duty Cycle Adjustment features?

1686 - What is the impact and potential problems when the reference clock input of the PLL in the FPGA is lower than the specification defined in datasheet?