3678 - PLL: When does the lock of PLL lose?

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• 873 - What types of issues could cause the PLL to lose lock?

  Situation: A CLKI input frequency to a PLL in a Lattice device is within the normal range for proper PLL operation, yet the PLL loses lock every now and then. Answer: As an example when using a LatticeXP2 device, check that the CLK signal that ...

• 793 - PLL: If the PLL loses lock after the LOCK signal has gone high/active, will the LOCK signal go low to indicate that the PLL has lost lock?

  Definition: The Lattice FPGA LatticeECP2, LatticeECP2M, LatticeECP3, LatticeSC all have PLL modules. The PLL module has a Lock signal indiating the status of the PLL. For some applications users may use this LOCK signal as a flag or control signal ...

• 2469 - LatticeECP3: Why does the PLL simulation model act differently than hardware?

  A PLL is mainly an analog circuit. Because of this, the PLL simulation model cannot operate in the same way as the hardware operates. The PLL simulation model also focuses on balancing a reasonable simulation time with actual hardware results. For ...

• Which power supplies are used by the PLL in Avant?

  The VCCA_PLL* and VCC are the power supplies connected to the PLL power rails.

• 1155 - Why won't the second PLL in a cascaded PLL design achieve lock during simulation?

  My design uses 2 PLLs that are cascaded; i.e the output of the 1st PLL is the input of the 2nd PLL. The 1st PLL functions fine in simulations but the 2nd PLL will not achieve lock and the output frequency is not correct. The input frequency of the ...